[llvm] [RISCV] Add branch+c.mv macrofusion for sifive-p450. (PR #76169)

[Wang Pengcheng via llvm-commits]

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@@ -112,6 +112,10 @@ def WriteFST16        : SchedWrite;    // Floating point sp store
 def WriteFST32        : SchedWrite;    // Floating point sp store
 def WriteFST64        : SchedWrite;    // Floating point dp store
 
+// CMOV for sifive-p450.
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wangpc-pp wrote:

This is intrusive, can we just use `InstRW` to override the resources in sifive-p450 schedule model? Or is it possible that we may reuse `WriteCMOV`/`ReadCMOV` someday? For example, `Zbt` is back to `Zb*` extensions.

https://github.com/llvm/llvm-project/pull/76169