[llvm] [AMDGPU] Allocate i1 argument to SGPRs (PR #72461)

[Jun Wang via llvm-commits]

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@@ -715,6 +715,14 @@ bool SILowerI1Copies::lowerCopiesToI1() {
       assert(!MI.getOperand(1).getSubReg());
 
       if (!SrcReg.isVirtual() || (!isLaneMaskReg(SrcReg) && !isVreg1(SrcReg))) {
+        if (!SrcReg.isVirtual() &&
+            TII->getRegisterInfo().getRegSizeInBits(SrcReg, *MRI) == 64) {
+          // When calling convention allocates SGPR for i1, for GPUs with
+          // wavefront size 64, i1 return value is put in 64b SGPR.
+          assert(ST->isWave64());
+          continue;
+        }
+
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jwanggit86 wrote:

The IR instruction callseq_end is always divergent. As a result, the CopyFromReg to copy the return value is also divergent. When the return type is i1, in the machine instruction, the dest reg would be vreg_1. In the above code in SILoweringI1Copies, we avoid lowing this COPY to avoid triggering the assert (code following assert assumes the src is a 32b phys reg).

https://github.com/llvm/llvm-project/pull/72461