[llvm] [CodeGen][MISched] Add misched post-regalloc bottom-up scheduling (PR #76186)

[via llvm-commits]

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``````````bash
git-clang-format --diff 058e527434aeb61ee6f72d2d460123440726a7df dbbba314dab2678748f02bbf75e9e409e39ecfc6 -- llvm/include/llvm/CodeGen/MachineScheduler.h llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h llvm/lib/CodeGen/MachineScheduler.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 7713305e50..7d6df2cc8d 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -93,8 +93,7 @@ cl::opt<MISchedPostRASched::Direction> PostRADirection(
     cl::init(MISchedPostRASched::TopDown),
     cl::values(clEnumValN(MISchedPostRASched::TopDown, "topdown",
                           "Force top-down post reg-alloc list scheduling"),
-               clEnumValN(MISchedPostRASched::BottomUp,
-                          "bottomup",
+               clEnumValN(MISchedPostRASched::BottomUp, "bottomup",
                           "Force bottom-up post reg-alloc list scheduling")));
 cl::opt<bool>
 DumpCriticalPathLength("misched-dcpl", cl::Hidden,

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https://github.com/llvm/llvm-project/pull/76186