[llvm] [AMDGPU] Global ISel for llvmi.prefetch (PR #76183)
Stanislav Mekhanoshin via llvm-commits
llvm-commits at lists.llvm.org
Thu Dec 21 13:06:29 PST 2023
https://github.com/rampitec created https://github.com/llvm/llvm-project/pull/76183
None
>From c78ad02368362e181b3a149f7b3baaf88eff1019 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: Thu, 21 Dec 2023 12:28:38 -0800
Subject: [PATCH] [AMDGPU] Global ISel for llvmi.prefetch
---
.../Target/GlobalISel/SelectionDAGCompat.td | 1 +
.../AMDGPU/AMDGPUInstructionSelector.cpp | 8 +-
.../Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 16 +-
llvm/lib/Target/AMDGPU/SMInstructions.td | 25 ++-
llvm/test/CodeGen/AMDGPU/llvm.prefetch.ll | 144 +++++++-----------
5 files changed, 90 insertions(+), 104 deletions(-)
diff --git a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
index f28c1edc3d95d8..5e704f0b9a758b 100644
--- a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
+++ b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
@@ -244,6 +244,7 @@ def : GINodeEquiv<G_ATOMICRMW_FMIN, atomic_load_fmin>;
def : GINodeEquiv<G_ATOMICRMW_UINC_WRAP, atomic_load_uinc_wrap>;
def : GINodeEquiv<G_ATOMICRMW_UDEC_WRAP, atomic_load_udec_wrap>;
def : GINodeEquiv<G_FENCE, atomic_fence>;
+def : GINodeEquiv<G_PREFETCH, prefetch>;
// Specifies the GlobalISel equivalents for SelectionDAG's ComplexPattern.
// Should be used on defs that subclass GIComplexOperandMatcher<>.
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 88ef4b5774242d..ad8dcda93c365a 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -2764,7 +2764,9 @@ static bool isConstant(const MachineInstr &MI) {
void AMDGPUInstructionSelector::getAddrModeInfo(const MachineInstr &Load,
const MachineRegisterInfo &MRI, SmallVectorImpl<GEPInfo> &AddrInfo) const {
- const MachineInstr *PtrMI = MRI.getUniqueVRegDef(Load.getOperand(1).getReg());
+ unsigned OpNo = Load.getOpcode() == AMDGPU::G_PREFETCH ? 0 : 1;
+ const MachineInstr *PtrMI =
+ MRI.getUniqueVRegDef(Load.getOperand(OpNo).getReg());
assert(PtrMI);
@@ -2817,6 +2819,10 @@ bool AMDGPUInstructionSelector::isInstrUniform(const MachineInstr &MI) const {
if (MMO->getAddrSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT)
return true;
+ if (MI.getOpcode() == AMDGPU::G_PREFETCH)
+ return RBI.getRegBank(MI.getOperand(0).getReg(), *MRI, TRI)->getID() ==
+ AMDGPU::SGPRRegBankID;
+
const Instruction *I = dyn_cast<Instruction>(Ptr);
return I && I->getMetadata("amdgpu.uniform");
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index c9412f720c62ec..dd160099a44014 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -3263,17 +3263,19 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
MI.eraseFromParent();
return;
}
- unsigned PtrBank =
- getRegBankID(MI.getOperand(0).getReg(), MRI, AMDGPU::SGPRRegBankID);
+ Register PtrReg = MI.getOperand(0).getReg();
+ unsigned PtrBank = getRegBankID(PtrReg, MRI, AMDGPU::SGPRRegBankID);
if (PtrBank == AMDGPU::VGPRRegBankID) {
MI.eraseFromParent();
return;
}
- // FIXME: There is currently no support for prefetch in global isel.
- // There is no node equivalence and what's worse there is no MMO produced
- // for a prefetch on global isel path.
- // Prefetch does not affect execution so erase it for now.
- MI.eraseFromParent();
+ unsigned AS = MRI.getType(PtrReg).getAddressSpace();
+ if (!AMDGPU::isFlatGlobalAddrSpace(AS) &&
+ AS != AMDGPUAS::CONSTANT_ADDRESS_32BIT) {
+ MI.eraseFromParent();
+ return;
+ }
+ applyDefaultMapping(OpdMapper);
return;
}
default:
diff --git a/llvm/lib/Target/AMDGPU/SMInstructions.td b/llvm/lib/Target/AMDGPU/SMInstructions.td
index 3297847b0360a9..be21cf0140fc85 100644
--- a/llvm/lib/Target/AMDGPU/SMInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SMInstructions.td
@@ -977,20 +977,35 @@ def : GCNPat <
}
} // let OtherPredicates = [HasShaderCyclesRegister]
-multiclass SMPrefetchPat<string type, int cache_type> {
+def i32imm_zero : TImmLeaf <i32, [{
+ return Imm == 0;
+}]>;
+
+def i32imm_one : TImmLeaf <i32, [{
+ return Imm == 1;
+}]>;
+
+multiclass SMPrefetchPat<string type, TImmLeaf cache_type> {
def : GCNPat <
- (smrd_prefetch (SMRDImm i64:$sbase, i32:$offset), timm, timm, (i32 cache_type)),
+ (smrd_prefetch (SMRDImm i64:$sbase, i32:$offset), timm, timm, cache_type),
(!cast<SM_Prefetch_Pseudo>("S_PREFETCH_"#type) $sbase, $offset, (i32 SGPR_NULL), (i8 0))
>;
def : GCNPat <
- (smrd_prefetch (i64 SReg_64:$sbase), timm, timm, (i32 cache_type)),
+ (smrd_prefetch (i64 SReg_64:$sbase), timm, timm, cache_type),
(!cast<SM_Prefetch_Pseudo>("S_PREFETCH_"#type) $sbase, 0, (i32 SGPR_NULL), (i8 0))
>;
+
+ def : GCNPat <
+ (smrd_prefetch (i32 SReg_32:$sbase), timm, timm, cache_type),
+ (!cast<SM_Prefetch_Pseudo>("S_PREFETCH_"#type)
+ (i64 (REG_SEQUENCE SReg_64, $sbase, sub0, (i32 (S_MOV_B32 (i32 0))), sub1)),
+ 0, (i32 SGPR_NULL), (i8 0))
+ >;
}
-defm : SMPrefetchPat<"INST", 0>;
-defm : SMPrefetchPat<"DATA", 1>;
+defm : SMPrefetchPat<"INST", i32imm_zero>;
+defm : SMPrefetchPat<"DATA", i32imm_one>;
//===----------------------------------------------------------------------===//
// GFX10.
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.prefetch.ll b/llvm/test/CodeGen/AMDGPU/llvm.prefetch.ll
index c287789f8f4938..dcf9b3f263ab68 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.prefetch.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.prefetch.ll
@@ -1,42 +1,34 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -march=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX12-SDAG %s
+; RUN: llc -march=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX12,GFX12-SDAG %s
; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX11 %s
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX12-GISEL %s
+; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX12,GFX12-GISEL %s
; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX11 %s
; Scalar data prefetch
define amdgpu_ps void @prefetch_data_sgpr(ptr addrspace(4) inreg %ptr) {
-; GFX12-SDAG-LABEL: prefetch_data_sgpr:
-; GFX12-SDAG: ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT: s_prefetch_data s[0:1], 0x0, null, 0
-; GFX12-SDAG-NEXT: s_endpgm
+; GFX12-LABEL: prefetch_data_sgpr:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_prefetch_data s[0:1], 0x0, null, 0
+; GFX12-NEXT: s_endpgm
;
; GFX11-LABEL: prefetch_data_sgpr:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_endpgm
-;
-; GFX12-GISEL-LABEL: prefetch_data_sgpr:
-; GFX12-GISEL: ; %bb.0: ; %entry
-; GFX12-GISEL-NEXT: s_endpgm
entry:
tail call void @llvm.prefetch.p4(ptr addrspace(4) %ptr, i32 0, i32 0, i32 1)
ret void
}
define amdgpu_ps void @prefetch_data_sgpr_offset(ptr addrspace(4) inreg %ptr) {
-; GFX12-SDAG-LABEL: prefetch_data_sgpr_offset:
-; GFX12-SDAG: ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT: s_prefetch_data s[0:1], 0x200, null, 0
-; GFX12-SDAG-NEXT: s_endpgm
+; GFX12-LABEL: prefetch_data_sgpr_offset:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_prefetch_data s[0:1], 0x200, null, 0
+; GFX12-NEXT: s_endpgm
;
; GFX11-LABEL: prefetch_data_sgpr_offset:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_endpgm
-;
-; GFX12-GISEL-LABEL: prefetch_data_sgpr_offset:
-; GFX12-GISEL: ; %bb.0: ; %entry
-; GFX12-GISEL-NEXT: s_endpgm
entry:
%gep = getelementptr float, ptr addrspace(4) %ptr, i32 128
tail call void @llvm.prefetch.p4(ptr addrspace(4) %gep, i32 0, i32 0, i32 1)
@@ -46,18 +38,14 @@ entry:
; Check large offsets
define amdgpu_ps void @prefetch_data_sgpr_max_offset(ptr addrspace(4) inreg %ptr) {
-; GFX12-SDAG-LABEL: prefetch_data_sgpr_max_offset:
-; GFX12-SDAG: ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT: s_prefetch_data s[0:1], 0x7fffff, null, 0
-; GFX12-SDAG-NEXT: s_endpgm
+; GFX12-LABEL: prefetch_data_sgpr_max_offset:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_prefetch_data s[0:1], 0x7fffff, null, 0
+; GFX12-NEXT: s_endpgm
;
; GFX11-LABEL: prefetch_data_sgpr_max_offset:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_endpgm
-;
-; GFX12-GISEL-LABEL: prefetch_data_sgpr_max_offset:
-; GFX12-GISEL: ; %bb.0: ; %entry
-; GFX12-GISEL-NEXT: s_endpgm
entry:
%gep = getelementptr i8, ptr addrspace(4) %ptr, i32 8388607
tail call void @llvm.prefetch.p4(ptr addrspace(4) %gep, i32 0, i32 0, i32 1)
@@ -65,18 +53,14 @@ entry:
}
define amdgpu_ps void @prefetch_data_sgpr_min_offset(ptr addrspace(4) inreg %ptr) {
-; GFX12-SDAG-LABEL: prefetch_data_sgpr_min_offset:
-; GFX12-SDAG: ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT: s_prefetch_data s[0:1], -0x800000, null, 0
-; GFX12-SDAG-NEXT: s_endpgm
+; GFX12-LABEL: prefetch_data_sgpr_min_offset:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_prefetch_data s[0:1], -0x800000, null, 0
+; GFX12-NEXT: s_endpgm
;
; GFX11-LABEL: prefetch_data_sgpr_min_offset:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_endpgm
-;
-; GFX12-GISEL-LABEL: prefetch_data_sgpr_min_offset:
-; GFX12-GISEL: ; %bb.0: ; %entry
-; GFX12-GISEL-NEXT: s_endpgm
entry:
%gep = getelementptr i8, ptr addrspace(4) %ptr, i32 -8388608
tail call void @llvm.prefetch.p4(ptr addrspace(4) %gep, i32 0, i32 0, i32 1)
@@ -96,6 +80,9 @@ define amdgpu_ps void @prefetch_data_sgpr_too_large_offset(ptr addrspace(4) inre
;
; GFX12-GISEL-LABEL: prefetch_data_sgpr_too_large_offset:
; GFX12-GISEL: ; %bb.0: ; %entry
+; GFX12-GISEL-NEXT: s_add_co_u32 s0, s0, 0x800000
+; GFX12-GISEL-NEXT: s_add_co_ci_u32 s1, s1, 0
+; GFX12-GISEL-NEXT: s_prefetch_data s[0:1], 0x0, null, 0
; GFX12-GISEL-NEXT: s_endpgm
entry:
%gep = getelementptr i8, ptr addrspace(4) %ptr, i32 8388608
@@ -137,55 +124,43 @@ entry:
; Check supported address spaces
define amdgpu_ps void @prefetch_data_sgpr_flat(ptr inreg %ptr) {
-; GFX12-SDAG-LABEL: prefetch_data_sgpr_flat:
-; GFX12-SDAG: ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT: s_prefetch_data s[0:1], 0x0, null, 0
-; GFX12-SDAG-NEXT: s_endpgm
+; GFX12-LABEL: prefetch_data_sgpr_flat:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_prefetch_data s[0:1], 0x0, null, 0
+; GFX12-NEXT: s_endpgm
;
; GFX11-LABEL: prefetch_data_sgpr_flat:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_endpgm
-;
-; GFX12-GISEL-LABEL: prefetch_data_sgpr_flat:
-; GFX12-GISEL: ; %bb.0: ; %entry
-; GFX12-GISEL-NEXT: s_endpgm
entry:
tail call void @llvm.prefetch.pf(ptr %ptr, i32 0, i32 0, i32 1)
ret void
}
define amdgpu_ps void @prefetch_data_sgpr_global(ptr addrspace(1) inreg %ptr) {
-; GFX12-SDAG-LABEL: prefetch_data_sgpr_global:
-; GFX12-SDAG: ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT: s_prefetch_data s[0:1], 0x0, null, 0
-; GFX12-SDAG-NEXT: s_endpgm
+; GFX12-LABEL: prefetch_data_sgpr_global:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_prefetch_data s[0:1], 0x0, null, 0
+; GFX12-NEXT: s_endpgm
;
; GFX11-LABEL: prefetch_data_sgpr_global:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_endpgm
-;
-; GFX12-GISEL-LABEL: prefetch_data_sgpr_global:
-; GFX12-GISEL: ; %bb.0: ; %entry
-; GFX12-GISEL-NEXT: s_endpgm
entry:
tail call void @llvm.prefetch.p1(ptr addrspace(1) %ptr, i32 0, i32 0, i32 1)
ret void
}
define amdgpu_ps void @prefetch_data_sgpr_constant_32bit(ptr addrspace(6) inreg %ptr) {
-; GFX12-SDAG-LABEL: prefetch_data_sgpr_constant_32bit:
-; GFX12-SDAG: ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT: s_mov_b32 s1, 0
-; GFX12-SDAG-NEXT: s_prefetch_data s[0:1], 0x0, null, 0
-; GFX12-SDAG-NEXT: s_endpgm
+; GFX12-LABEL: prefetch_data_sgpr_constant_32bit:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_mov_b32 s1, 0
+; GFX12-NEXT: s_prefetch_data s[0:1], 0x0, null, 0
+; GFX12-NEXT: s_endpgm
;
; GFX11-LABEL: prefetch_data_sgpr_constant_32bit:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_endpgm
-;
-; GFX12-GISEL-LABEL: prefetch_data_sgpr_constant_32bit:
-; GFX12-GISEL: ; %bb.0: ; %entry
-; GFX12-GISEL-NEXT: s_endpgm
entry:
tail call void @llvm.prefetch.p6(ptr addrspace(6) %ptr, i32 0, i32 0, i32 1)
ret void
@@ -194,36 +169,28 @@ entry:
; I$ prefetch
define amdgpu_ps void @prefetch_inst_sgpr(ptr addrspace(4) inreg %ptr) {
-; GFX12-SDAG-LABEL: prefetch_inst_sgpr:
-; GFX12-SDAG: ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT: s_prefetch_inst s[0:1], 0x0, null, 0
-; GFX12-SDAG-NEXT: s_endpgm
+; GFX12-LABEL: prefetch_inst_sgpr:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_prefetch_inst s[0:1], 0x0, null, 0
+; GFX12-NEXT: s_endpgm
;
; GFX11-LABEL: prefetch_inst_sgpr:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_endpgm
-;
-; GFX12-GISEL-LABEL: prefetch_inst_sgpr:
-; GFX12-GISEL: ; %bb.0: ; %entry
-; GFX12-GISEL-NEXT: s_endpgm
entry:
tail call void @llvm.prefetch.p4(ptr addrspace(4) %ptr, i32 0, i32 0, i32 0)
ret void
}
define amdgpu_ps void @prefetch_inst_sgpr_offset(ptr addrspace(4) inreg %ptr) {
-; GFX12-SDAG-LABEL: prefetch_inst_sgpr_offset:
-; GFX12-SDAG: ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT: s_prefetch_inst s[0:1], 0x80, null, 0
-; GFX12-SDAG-NEXT: s_endpgm
+; GFX12-LABEL: prefetch_inst_sgpr_offset:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_prefetch_inst s[0:1], 0x80, null, 0
+; GFX12-NEXT: s_endpgm
;
; GFX11-LABEL: prefetch_inst_sgpr_offset:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_endpgm
-;
-; GFX12-GISEL-LABEL: prefetch_inst_sgpr_offset:
-; GFX12-GISEL: ; %bb.0: ; %entry
-; GFX12-GISEL-NEXT: s_endpgm
entry:
%gep = getelementptr i8, ptr addrspace(4) %ptr, i32 128
tail call void @llvm.prefetch.p4(ptr addrspace(4) %gep, i32 0, i32 0, i32 0)
@@ -233,18 +200,14 @@ entry:
; Check large offsets
define amdgpu_ps void @prefetch_inst_sgpr_max_offset(ptr addrspace(4) inreg %ptr) {
-; GFX12-SDAG-LABEL: prefetch_inst_sgpr_max_offset:
-; GFX12-SDAG: ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT: s_prefetch_inst s[0:1], 0x7fffff, null, 0
-; GFX12-SDAG-NEXT: s_endpgm
+; GFX12-LABEL: prefetch_inst_sgpr_max_offset:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_prefetch_inst s[0:1], 0x7fffff, null, 0
+; GFX12-NEXT: s_endpgm
;
; GFX11-LABEL: prefetch_inst_sgpr_max_offset:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_endpgm
-;
-; GFX12-GISEL-LABEL: prefetch_inst_sgpr_max_offset:
-; GFX12-GISEL: ; %bb.0: ; %entry
-; GFX12-GISEL-NEXT: s_endpgm
entry:
%gep = getelementptr i8, ptr addrspace(4) %ptr, i32 8388607
tail call void @llvm.prefetch.p4(ptr addrspace(4) %gep, i32 0, i32 0, i32 0)
@@ -252,18 +215,14 @@ entry:
}
define amdgpu_ps void @prefetch_inst_sgpr_min_offset(ptr addrspace(4) inreg %ptr) {
-; GFX12-SDAG-LABEL: prefetch_inst_sgpr_min_offset:
-; GFX12-SDAG: ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT: s_prefetch_inst s[0:1], -0x800000, null, 0
-; GFX12-SDAG-NEXT: s_endpgm
+; GFX12-LABEL: prefetch_inst_sgpr_min_offset:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_prefetch_inst s[0:1], -0x800000, null, 0
+; GFX12-NEXT: s_endpgm
;
; GFX11-LABEL: prefetch_inst_sgpr_min_offset:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_endpgm
-;
-; GFX12-GISEL-LABEL: prefetch_inst_sgpr_min_offset:
-; GFX12-GISEL: ; %bb.0: ; %entry
-; GFX12-GISEL-NEXT: s_endpgm
entry:
%gep = getelementptr i8, ptr addrspace(4) %ptr, i32 -8388608
tail call void @llvm.prefetch.p4(ptr addrspace(4) %gep, i32 0, i32 0, i32 0)
@@ -283,6 +242,9 @@ define amdgpu_ps void @prefetch_inst_sgpr_too_large_offset(ptr addrspace(4) inre
;
; GFX12-GISEL-LABEL: prefetch_inst_sgpr_too_large_offset:
; GFX12-GISEL: ; %bb.0: ; %entry
+; GFX12-GISEL-NEXT: s_add_co_u32 s0, s0, 0x800000
+; GFX12-GISEL-NEXT: s_add_co_ci_u32 s1, s1, 0
+; GFX12-GISEL-NEXT: s_prefetch_inst s[0:1], 0x0, null, 0
; GFX12-GISEL-NEXT: s_endpgm
entry:
%gep = getelementptr i8, ptr addrspace(4) %ptr, i32 8388608
More information about the llvm-commits
mailing list