[llvm] [AArch64] Assembly support for the Armv9.5-A RAS Extensions (PR #76161)

[Lucas Duarte Prates via llvm-commits]

https://github.com/pratlucas created https://github.com/llvm/llvm-project/pull/76161

This implements assembly support for the RAS extensions introduced as
part of the Armv9.5-A architecture version.
The changes include:
* New system registers for Delegated SError exceptions for EL3 (FEAT_E3DSE):
  * VDISR_EL3
  * VSESR_EL3

Mode details about these extensions can be found at:
    * https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2023
    * https://developer.arm.com/documentation/ddi0602/2023-09/

Co-authored-by: Jirui Wu <jirui.wu at arm.com>
Co-authored-by: Oliver Stannard <oliver.stannard at arm.com>


>From fd12bd3ef128b207e0415ec3afd27e415032e9b9 Mon Sep 17 00:00:00 2001
From: Lucas Prates <lucas.prates at arm.com>
Date: Thu, 21 Dec 2023 14:32:11 +0000
Subject: [PATCH] [AArch64] Assembly support for the Armv9.5-A RAS Extensions

This implements assembly support for the RAS extensions introduced as
part of the Armv9.5-A architecture version.
The changes include:
* New system registers for Delegated SError exceptions for EL3 (FEAT_E3DSE):
  * VDISR_EL3
  * VSESR_EL3

Mode details about these extensions can be found at:
    * https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2023
    * https://developer.arm.com/documentation/ddi0602/2023-09/

Co-authored-by: Jirui Wu <jirui.wu at arm.com>
Co-authored-by: Oliver Stannard <oliver.stannard at arm.com>
---
 llvm/lib/Target/AArch64/AArch64SystemOperands.td    |  5 +++++
 llvm/test/MC/AArch64/armv9.5a-e3dse.s               | 13 +++++++++++++
 .../test/MC/Disassembler/AArch64/armv9.5a-e3dse.txt | 13 +++++++++++++
 3 files changed, 31 insertions(+)
 create mode 100644 llvm/test/MC/AArch64/armv9.5a-e3dse.s
 create mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.5a-e3dse.txt

diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index e8b5f6059c9ee6..28a5776a3089cf 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -1946,3 +1946,8 @@ def : RWSysReg<"MDSTEPOP_EL1",      0b10, 0b000, 0b0000, 0b0101, 0b010>;
 // v9.5a System PMU zero register (FEAT_SPMU2)
 //                                  Op0   Op1    CRn     CRm     Op2
 def : WOSysReg<"SPMZR_EL0",         0b10, 0b011, 0b1001, 0b1100, 0b100>;
+
+// v9.5a Delegated SError exceptions for EL3 (FEAT_E3DSE)
+//                                  Op0   Op1    CRn     CRm     Op2
+def : RWSysReg<"VDISR_EL3",         0b11, 0b110, 0b1100, 0b0001, 0b001>;
+def : RWSysReg<"VSESR_EL3",         0b11, 0b110, 0b0101, 0b0010, 0b011>;
diff --git a/llvm/test/MC/AArch64/armv9.5a-e3dse.s b/llvm/test/MC/AArch64/armv9.5a-e3dse.s
new file mode 100644
index 00000000000000..b69d49ab4e9e52
--- /dev/null
+++ b/llvm/test/MC/AArch64/armv9.5a-e3dse.s
@@ -0,0 +1,13 @@
+// RUN: llvm-mc -triple aarch64 -show-encoding < %s | FileCheck %s
+
+mrs x0, VDISR_EL3
+// CHECK: mrs x0, VDISR_EL3                  // encoding: [0x20,0xc1,0x3e,0xd5]
+
+msr VDISR_EL3, x0
+// CHECK: msr VDISR_EL3, x0                  // encoding: [0x20,0xc1,0x1e,0xd5]
+
+mrs x0, VSESR_EL3
+// CHECK: mrs x0, VSESR_EL3                  // encoding: [0x60,0x52,0x3e,0xd5]
+
+msr VSESR_EL3, x0
+// CHECK: msr VSESR_EL3, x0                  // encoding: [0x60,0x52,0x1e,0xd5]
diff --git a/llvm/test/MC/Disassembler/AArch64/armv9.5a-e3dse.txt b/llvm/test/MC/Disassembler/AArch64/armv9.5a-e3dse.txt
new file mode 100644
index 00000000000000..d2476dbf876d4c
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AArch64/armv9.5a-e3dse.txt
@@ -0,0 +1,13 @@
+# RUN: llvm-mc -triple aarch64 -disassemble < %s | FileCheck %s
+
+[0x20,0xc1,0x3e,0xd5]
+# CHECK: mrs x0, VDISR_EL3
+
+[0x20,0xc1,0x1e,0xd5]
+# CHECK: msr VDISR_EL3, x0
+
+[0x60,0x52,0x3e,0xd5]
+# CHECK: mrs x0, VSESR_EL3
+
+[0x60,0x52,0x1e,0xd5]
+# CHECK: msr VSESR_EL3, x0