[llvm] 4bad0cb - [AArch64] Precommit tests for PR75343, NFC
via llvm-commits
llvm-commits at lists.llvm.org
Thu Dec 21 02:56:36 PST 2023
Author: zhongyunde 00443407
Date: 2023-12-21T18:54:14+08:00
New Revision: 4bad0cb359d3066fb29f589e408a5b812a628896
URL: https://github.com/llvm/llvm-project/commit/4bad0cb359d3066fb29f589e408a5b812a628896
DIFF: https://github.com/llvm/llvm-project/commit/4bad0cb359d3066fb29f589e408a5b812a628896.diff
LOG: [AArch64] Precommit tests for PR75343, NFC
Added:
llvm/test/CodeGen/AArch64/large-offset-ldr-merge.mir
Modified:
llvm/test/CodeGen/AArch64/arm64-addrmode.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/arm64-addrmode.ll b/llvm/test/CodeGen/AArch64/arm64-addrmode.ll
index 3d4749a7b8e7df..d39029163a47aa 100644
--- a/llvm/test/CodeGen/AArch64/arm64-addrmode.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-addrmode.ll
@@ -210,12 +210,26 @@ define void @t17(i64 %a) {
ret void
}
-define i32 @LdOffset_i8(ptr %a) {
+; LDRBBroX
+define i8 @LdOffset_i8(ptr %a) {
; CHECK-LABEL: LdOffset_i8:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #56952 // =0xde78
; CHECK-NEXT: movk w8, #15, lsl #16
; CHECK-NEXT: ldrb w0, [x0, x8]
+; CHECK-NEXT: ret
+ %arrayidx = getelementptr inbounds i8, ptr %a, i64 1039992
+ %val = load i8, ptr %arrayidx, align 1
+ ret i8 %val
+}
+
+; LDRBBroX
+define i32 @LdOffset_i8_zext32(ptr %a) {
+; CHECK-LABEL: LdOffset_i8_zext32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #56952 // =0xde78
+; CHECK-NEXT: movk w8, #15, lsl #16
+; CHECK-NEXT: ldrb w0, [x0, x8]
; CHECK-NEXT: ret
%arrayidx = getelementptr inbounds i8, ptr %a, i64 1039992
%val = load i8, ptr %arrayidx, align 1
@@ -223,11 +237,81 @@ define i32 @LdOffset_i8(ptr %a) {
ret i32 %conv
}
-define i32 @LdOffset_i16(ptr %a) {
+; LDRSBWroX
+define i32 @LdOffset_i8_sext32(ptr %a) {
+; CHECK-LABEL: LdOffset_i8_sext32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #56952 // =0xde78
+; CHECK-NEXT: movk w8, #15, lsl #16
+; CHECK-NEXT: ldrsb w0, [x0, x8]
+; CHECK-NEXT: ret
+ %arrayidx = getelementptr inbounds i8, ptr %a, i64 1039992
+ %val = load i8, ptr %arrayidx, align 1
+ %conv = sext i8 %val to i32
+ ret i32 %conv
+}
+
+; LDRBBroX
+define i64 @LdOffset_i8_zext64(ptr %a) {
+; CHECK-LABEL: LdOffset_i8_zext64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #56952 // =0xde78
+; CHECK-NEXT: movk w8, #15, lsl #16
+; CHECK-NEXT: ldrb w0, [x0, x8]
+; CHECK-NEXT: ret
+ %arrayidx = getelementptr inbounds i8, ptr %a, i64 1039992
+ %val = load i8, ptr %arrayidx, align 1
+ %conv = zext i8 %val to i64
+ ret i64 %conv
+}
+
+; LDRSBXroX
+define i64 @LdOffset_i8_sext64(ptr %a) {
+; CHECK-LABEL: LdOffset_i8_sext64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #56952 // =0xde78
+; CHECK-NEXT: movk w8, #15, lsl #16
+; CHECK-NEXT: ldrsb x0, [x0, x8]
+; CHECK-NEXT: ret
+ %arrayidx = getelementptr inbounds i8, ptr %a, i64 1039992
+ %val = load i8, ptr %arrayidx, align 1
+ %conv = sext i8 %val to i64
+ ret i64 %conv
+}
+
+; LDRHHroX
+define i16 @LdOffset_i16(ptr %a) {
; CHECK-LABEL: LdOffset_i16:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #48368 // =0xbcf0
; CHECK-NEXT: movk w8, #31, lsl #16
+; CHECK-NEXT: ldrh w0, [x0, x8]
+; CHECK-NEXT: ret
+ %arrayidx = getelementptr inbounds i16, ptr %a, i64 1039992
+ %val = load i16, ptr %arrayidx, align 2
+ ret i16 %val
+}
+
+; LDRHHroX
+define i32 @LdOffset_i16_zext32(ptr %a) {
+; CHECK-LABEL: LdOffset_i16_zext32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #48368 // =0xbcf0
+; CHECK-NEXT: movk w8, #31, lsl #16
+; CHECK-NEXT: ldrh w0, [x0, x8]
+; CHECK-NEXT: ret
+ %arrayidx = getelementptr inbounds i16, ptr %a, i64 1039992
+ %val = load i16, ptr %arrayidx, align 2
+ %conv = zext i16 %val to i32
+ ret i32 %conv
+}
+
+; LDRSHWroX
+define i32 @LdOffset_i16_sext32(ptr %a) {
+; CHECK-LABEL: LdOffset_i16_sext32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #48368 // =0xbcf0
+; CHECK-NEXT: movk w8, #31, lsl #16
; CHECK-NEXT: ldrsh w0, [x0, x8]
; CHECK-NEXT: ret
%arrayidx = getelementptr inbounds i16, ptr %a, i64 1039992
@@ -236,6 +320,35 @@ define i32 @LdOffset_i16(ptr %a) {
ret i32 %conv
}
+; LDRHHroX
+define i64 @LdOffset_i16_zext64(ptr %a) {
+; CHECK-LABEL: LdOffset_i16_zext64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #48368 // =0xbcf0
+; CHECK-NEXT: movk w8, #31, lsl #16
+; CHECK-NEXT: ldrh w0, [x0, x8]
+; CHECK-NEXT: ret
+ %arrayidx = getelementptr inbounds i16, ptr %a, i64 1039992
+ %val = load i16, ptr %arrayidx, align 2
+ %conv = zext i16 %val to i64
+ ret i64 %conv
+}
+
+; LDRSHXroX
+define i64 @LdOffset_i16_sext64(ptr %a) {
+; CHECK-LABEL: LdOffset_i16_sext64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #48368 // =0xbcf0
+; CHECK-NEXT: movk w8, #31, lsl #16
+; CHECK-NEXT: ldrsh x0, [x0, x8]
+; CHECK-NEXT: ret
+ %arrayidx = getelementptr inbounds i16, ptr %a, i64 1039992
+ %val = load i16, ptr %arrayidx, align 2
+ %conv = sext i16 %val to i64
+ ret i64 %conv
+}
+
+; LDRWroX
define i32 @LdOffset_i32(ptr %a) {
; CHECK-LABEL: LdOffset_i32:
; CHECK: // %bb.0:
@@ -248,6 +361,133 @@ define i32 @LdOffset_i32(ptr %a) {
ret i32 %val
}
+; LDRWroX
+define i64 @LdOffset_i32_zext64(ptr %a) {
+; CHECK-LABEL: LdOffset_i32_zext64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #31200 // =0x79e0
+; CHECK-NEXT: movk w8, #63, lsl #16
+; CHECK-NEXT: ldr w0, [x0, x8]
+; CHECK-NEXT: ret
+ %arrayidx = getelementptr inbounds i32, ptr %a, i64 1039992
+ %val = load i32, ptr %arrayidx, align 2
+ %conv = zext i32 %val to i64
+ ret i64 %conv
+}
+
+; LDRSWroX
+define i64 @LdOffset_i32_sext64(ptr %a) {
+; CHECK-LABEL: LdOffset_i32_sext64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #31200 // =0x79e0
+; CHECK-NEXT: movk w8, #63, lsl #16
+; CHECK-NEXT: ldrsw x0, [x0, x8]
+; CHECK-NEXT: ret
+ %arrayidx = getelementptr inbounds i32, ptr %a, i64 1039992
+ %val = load i32, ptr %arrayidx, align 2
+ %conv = sext i32 %val to i64
+ ret i64 %conv
+}
+
+; LDRXroX
+define i64 @LdOffset_i64(ptr %a) {
+; CHECK-LABEL: LdOffset_i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #62400 // =0xf3c0
+; CHECK-NEXT: movk w8, #126, lsl #16
+; CHECK-NEXT: ldr x0, [x0, x8]
+; CHECK-NEXT: ret
+ %arrayidx = getelementptr inbounds i64, ptr %a, i64 1039992
+ %val = load i64, ptr %arrayidx, align 4
+ ret i64 %val
+}
+
+; LDRDroX
+define <2 x i32> @LdOffset_v2i32(ptr %a) {
+; CHECK-LABEL: LdOffset_v2i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #62400 // =0xf3c0
+; CHECK-NEXT: movk w8, #126, lsl #16
+; CHECK-NEXT: ldr d0, [x0, x8]
+; CHECK-NEXT: ret
+ %arrayidx = getelementptr inbounds <2 x i32>, ptr %a, i64 1039992
+ %val = load <2 x i32>, ptr %arrayidx, align 4
+ ret <2 x i32> %val
+}
+
+; LDRQroX
+define <2 x i64> @LdOffset_v2i64(ptr %a) {
+; CHECK-LABEL: LdOffset_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #59264 // =0xe780
+; CHECK-NEXT: movk w8, #253, lsl #16
+; CHECK-NEXT: ldr q0, [x0, x8]
+; CHECK-NEXT: ret
+ %arrayidx = getelementptr inbounds <2 x i64>, ptr %a, i64 1039992
+ %val = load <2 x i64>, ptr %arrayidx, align 4
+ ret <2 x i64> %val
+}
+
+; LDRSBWroX
+define double @LdOffset_i8_f64(ptr %a) {
+; CHECK-LABEL: LdOffset_i8_f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #56952 // =0xde78
+; CHECK-NEXT: movk w8, #15, lsl #16
+; CHECK-NEXT: ldrsb w8, [x0, x8]
+; CHECK-NEXT: scvtf d0, w8
+; CHECK-NEXT: ret
+ %arrayidx = getelementptr inbounds i8, ptr %a, i64 1039992
+ %val = load i8, ptr %arrayidx, align 1
+ %conv = sitofp i8 %val to double
+ ret double %conv
+}
+
+; LDRSHWroX
+define double @LdOffset_i16_f64(ptr %a) {
+; CHECK-LABEL: LdOffset_i16_f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #48368 // =0xbcf0
+; CHECK-NEXT: movk w8, #31, lsl #16
+; CHECK-NEXT: ldrsh w8, [x0, x8]
+; CHECK-NEXT: scvtf d0, w8
+; CHECK-NEXT: ret
+ %arrayidx = getelementptr inbounds i16, ptr %a, i64 1039992
+ %val = load i16, ptr %arrayidx, align 2
+ %conv = sitofp i16 %val to double
+ ret double %conv
+}
+
+; LDRSroX
+define double @LdOffset_i32_f64(ptr %a) {
+; CHECK-LABEL: LdOffset_i32_f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #31200 // =0x79e0
+; CHECK-NEXT: movk w8, #63, lsl #16
+; CHECK-NEXT: ldr s0, [x0, x8]
+; CHECK-NEXT: ucvtf d0, d0
+; CHECK-NEXT: ret
+ %arrayidx = getelementptr inbounds i32, ptr %a, i64 1039992
+ %val = load i32, ptr %arrayidx, align 4
+ %conv = uitofp i32 %val to double
+ ret double %conv
+}
+
+; LDRDroX
+define double @LdOffset_i64_f64(ptr %a) {
+; CHECK-LABEL: LdOffset_i64_f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #62400 // =0xf3c0
+; CHECK-NEXT: movk w8, #126, lsl #16
+; CHECK-NEXT: ldr d0, [x0, x8]
+; CHECK-NEXT: scvtf d0, d0
+; CHECK-NEXT: ret
+ %arrayidx = getelementptr inbounds i64, ptr %a, i64 1039992
+ %val = load i64, ptr %arrayidx, align 8
+ %conv = sitofp i64 %val to double
+ ret double %conv
+}
+
define i64 @LdOffset_i64_multi_offset(ptr %a) {
; CHECK-LABEL: LdOffset_i64_multi_offset:
; CHECK: // %bb.0:
@@ -295,3 +535,27 @@ define i32 @LdOffset_i16_odd_offset(ptr nocapture noundef readonly %a) {
ret i32 %conv
}
+; Already encoded with a single mov MOVNWi
+define i8 @LdOffset_i8_movnwi(ptr %a) {
+; CHECK-LABEL: LdOffset_i8_movnwi:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #16777215 // =0xffffff
+; CHECK-NEXT: ldrb w0, [x0, x8]
+; CHECK-NEXT: ret
+ %arrayidx = getelementptr inbounds i8, ptr %a, i64 16777215
+ %val = load i8, ptr %arrayidx, align 1
+ ret i8 %val
+}
+
+; Negative test: the offset is too large to encoded with a add
+define i8 @LdOffset_i8_too_large(ptr %a) {
+; CHECK-LABEL: LdOffset_i8_too_large:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #1 // =0x1
+; CHECK-NEXT: movk w8, #256, lsl #16
+; CHECK-NEXT: ldrb w0, [x0, x8]
+; CHECK-NEXT: ret
+ %arrayidx = getelementptr inbounds i8, ptr %a, i64 16777217
+ %val = load i8, ptr %arrayidx, align 1
+ ret i8 %val
+}
diff --git a/llvm/test/CodeGen/AArch64/large-offset-ldr-merge.mir b/llvm/test/CodeGen/AArch64/large-offset-ldr-merge.mir
new file mode 100755
index 00000000000000..488f1ffdb52f3b
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/large-offset-ldr-merge.mir
@@ -0,0 +1,48 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64 -run-pass aarch64-ldst-opt %s -o - | FileCheck %s
+
+
+---
+name: LdOffset
+tracksRegLiveness: true
+liveins:
+ - { reg: '$x0', virtual-reg: '' }
+body: |
+ bb.0.entry:
+ liveins: $x0
+
+ ; CHECK-LABEL: name: LdOffset
+ ; CHECK: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $w8 = MOVZWi 56952, 0
+ ; CHECK-NEXT: renamable $w8 = MOVKWi $w8, 15, 16, implicit-def $x8
+ ; CHECK-NEXT: renamable $w0 = LDRBBroX killed renamable $x0, killed renamable $x8, 0, 0
+ ; CHECK-NEXT: RET undef $lr, implicit $w0
+ renamable $w8 = MOVZWi 56952, 0
+ renamable $w8 = MOVKWi $w8, 15, 16, implicit-def $x8
+ renamable $w0 = LDRBBroX killed renamable $x0, killed renamable $x8, 0, 0
+ RET undef $lr, implicit $w0
+...
+
+# Negative test: the IndexReg missing killed flags
+---
+name: LdOffset_missing_killed
+tracksRegLiveness: true
+liveins:
+ - { reg: '$x0', virtual-reg: '' }
+body: |
+ bb.0.entry:
+ liveins: $x0
+
+ ; CHECK-LABEL: name: LdOffset_missing_killed
+ ; CHECK: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $w8 = MOVZWi 56952, 0
+ ; CHECK-NEXT: renamable $w8 = MOVKWi $w8, 15, 16, implicit-def $x8
+ ; CHECK-NEXT: renamable $w0 = LDRBBroX killed renamable $x0, renamable $x8, 0, 0
+ ; CHECK-NEXT: RET undef $lr, implicit $w0
+ renamable $w8 = MOVZWi 56952, 0
+ renamable $w8 = MOVKWi $w8, 15, 16, implicit-def $x8
+ renamable $w0 = LDRBBroX killed renamable $x0, renamable $x8, 0, 0
+ RET undef $lr, implicit $w0
+...
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