[llvm] [RISCV] Split TuneShiftedZExtFusion (PR #76032)

[Mikhail Gudim via llvm-commits]

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@@ -977,9 +977,19 @@ def TuneLUIADDIFusion
 def TuneAUIPCADDIFusion
     : SubtargetFeature<"auipc-addi-fusion", "HasAUIPCADDIFusion",
                        "true", "Enable AUIPC+ADDI macrofusion">;
-def TuneShiftedZExtFusion
-    : SubtargetFeature<"shifted-zext-fusion", "HasShiftedZExtFusion",
-                       "true", "Enable SLLI+SRLI to be fused when computing (shifted) zero extension">;
+
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mgudim wrote:

I don't think "word" is the right word here ) Machine word on riscv64 is 64 bits. How about `ZExt16` and `ZExt32` instead?

https://github.com/llvm/llvm-project/pull/76032