[llvm] improve performance of Module Analysis stage in the part of processing "other instructions" (PR #76047)

[Michal Paszkowski via llvm-commits]

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@@ -319,15 +291,42 @@ void SPIRVModuleAnalysis::collectFuncNames(MachineInstr &MI,
   }
 }
 
+using InstrSignature = SmallVector<size_t>;
+using InstrTraces = std::set<InstrSignature>;
+
+// Returns a representation of an instruction as a vector of MachineOperand
+// hash values, see llvm::hash_value(const MachineOperand &MO) for details.
+// This creates a signature of the instruction with the same content
+// that MachineOperand::isIdenticalTo uses for comparison.
+static InstrSignature instrToSignature(MachineInstr &MI,
+                                       SPIRV::ModuleAnalysisInfo &MAI) {
+  InstrSignature ret;
+  for (unsigned i = 0; i < MI.getNumOperands(); ++i) {
+    const MachineOperand &MO = MI.getOperand(i);
+    size_t h;
+    if (MO.isReg()) {
+      Register RegAlias = MAI.getRegisterAlias(MI.getMF(), MO.getReg());
+      // mimic llvm::hash_value(const MachineOperand &MO)
+      h = hash_combine(MO.getType(), (unsigned)RegAlias, MO.getSubReg(),
+                       MO.isDef());
+    } else
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michalpaszkowski wrote:

Please add braces to the `else` block to keep it uniform with the main `if` clause/avoid confusion ([LLVM Coding Standards](https://llvm.org/docs/CodingStandards.html#:~:text=//%20Use%20braces%20for%20the%20%60if%60%20block%20to%20keep%20it%20uniform%20with%20the%20%60else%60%20block.))

https://github.com/llvm/llvm-project/pull/76047