[llvm] improve performance of Module Analysis stage in the part of processing "other instructions" (PR #76047)

[Vyacheslav Levytskyy via llvm-commits]

VyacheslavLevytskyy wrote:

@michalpaszkowski This is one possible way to fix the only timeout case from test cases of https://github.com/KhronosGroup/SPIRV-LLVM-Translator/tree/main/test 

https://github.com/llvm/llvm-project/pull/76047