[llvm] [RISCV] Rematerialize load (PR #73924)

[Niwin Anto via llvm-commits]

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@@ -626,7 +626,7 @@ def BGE  : BranchCC_rri<0b101, "bge">;
 def BLTU : BranchCC_rri<0b110, "bltu">;
 def BGEU : BranchCC_rri<0b111, "bgeu">;
 
-let IsSignExtendingOpW = 1 in {
+let IsSignExtendingOpW = 1, isReMaterializable = 1 in {
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niwinanto wrote:

Started a new discourse topic to discuss this issue. https://discourse.llvm.org/t/rematerialized-virtual-register-ran-out-of-registers-during-register-allocation/75774 

https://github.com/llvm/llvm-project/pull/73924