[llvm] bbe6c81 - [RISCV] Add missing REQUIRES asserts to test (NFC)

[Nikita Popov via llvm-commits]

Author: Nikita Popov
Date: 2023-12-20T09:42:14+01:00
New Revision: bbe6c81f808093c4030d7904136ff2f9dad6e73b

URL: https://github.com/llvm/llvm-project/commit/bbe6c81f808093c4030d7904136ff2f9dad6e73b
DIFF: https://github.com/llvm/llvm-project/commit/bbe6c81f808093c4030d7904136ff2f9dad6e73b.diff

LOG: [RISCV] Add missing REQUIRES asserts to test (NFC)

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/sifive7-enable-intervals.mir

Removed: 
    


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diff  --git a/llvm/test/CodeGen/RISCV/sifive7-enable-intervals.mir b/llvm/test/CodeGen/RISCV/sifive7-enable-intervals.mir
index 68e8c9e55ff3b8..e179e7f08752a8 100644
--- a/llvm/test/CodeGen/RISCV/sifive7-enable-intervals.mir
+++ b/llvm/test/CodeGen/RISCV/sifive7-enable-intervals.mir
@@ -1,6 +1,7 @@
 # RUN: llc -mtriple=riscv64 -mcpu=sifive-x280 -run-pass=machine-scheduler      \
 # RUN:  -debug-only=machine-scheduler -misched-dump-schedule-trace             \
 # RUN:  -misched-topdown -o - %s 2>&1 | FileCheck %s
+# REQUIRES: asserts
 
 # The purpose of this test is to show that the VADD instructions are issued so
 # that the SiFive7VA is saturated.