[llvm] [RISCV] Add missing lmul info for SiFive extensions (PR #76006)

Brandon Wu via llvm-commits llvm-commits at lists.llvm.org
Tue Dec 19 22:42:53 PST 2023

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https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/76006

Previous message: [llvm] [RISCV] Add missing lmul info for SiFive extensions (PR #76006)
Next message: [llvm] [ASAN][AMDGPU] Make address sanitizer checks more efficient for the divergent target. (PR #72247)
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