[llvm] [AMDGPU,test] Change llc -march= to -mtriple= (PR #75982)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 19 15:27:29 PST 2023
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Fangrui Song (MaskRay)
<details>
<summary>Changes</summary>
Similar to 806761a7629df268c8aed49657aeccffa6bca449.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
---
Patch is 2.06 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/75982.diff
1985 Files Affected:
- (modified) llvm/test/CodeGen/AMDGPU/32-bit-local-address-space.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/addo.ll (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-prelegalizer-combiner-crash.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-no-rtn.ll (+5-5)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-rtn.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f64.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-no-rtn.ll (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-rtn.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fabs-fneg.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-fma.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-mul.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul-post-legalize.mir (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul-pre-legalize.mir (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul.ll (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-mul.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-neg-mul.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-mul.ll (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-neg-mul.ll (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-unmerge-values.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-foldable-fneg.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsh.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsub-fneg.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-or-redundant.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-and.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-neg.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rot.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rsq.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rsq.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain-illegal-types.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain-shlsat.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic-shlsat.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-shift.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/dereferenceable-declaration.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll (+10-10)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll (+12-12)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll (+10-10)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.f32.ll (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.f64.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.v2f16.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll (+5-5)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll (+5-5)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fp-atomics-gfx940.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll (+5-5)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-no-rtn.ll (+5-5)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-rtn.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f64.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.v2f16-no-rtn.ll (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.v2f16-rtn.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-abs.mir (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir (+5-5)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.s16.mir (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.s16.mir (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.s16.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pk.i16.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pk.u16.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pknorm.i16.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pknorm.u16.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pkrtz.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.ds.swizzle.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.exp.compr.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.exp.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fcmp.constants.w32.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fcmp.constants.w64.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmad.ftz.mir (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.s16.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.s16.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mbcnt.lo.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mul.u24.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mulhi.i24.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mulhi.u24.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.legacy.mir (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.s16.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.readfirstlane.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.reloc.constant.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.clamp.mir (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.legacy.mir (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.s16.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.s.barrier.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.s.sendmsg.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sffbh.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.s16.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-flat.mir (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-global.mir (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbh-u32.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbl-b32.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-wave-address.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.s16.mir (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.v2s16.mir (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomic-cmpxchg-local.mir (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomic-cmpxchg-region.mir (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-add-flat.mir (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-add-global.mir (+7-7)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-fadd-local.mir (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-fadd-region.mir (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-xchg-local.mir (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-xchg-region.mir (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bitcast.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bitreverse.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-br.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bswap.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctlz-zero-undef.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctpop.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-cttz-zero-undef.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract-vector-elt.mir (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir (+5-5)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s16.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s32.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s64.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcanonicalize.mir (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.s16.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.mir (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.mir (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fconstant.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fexp2.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s16.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s32.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s64.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fma.s32.mir (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmad.s32.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.s16.mir (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.v2s16.mir (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.s16.mir (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.v2s16.mir (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.s16.mir (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.v2s16.mir (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.s16.mir (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.v2s16.mir (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.v2s16.mir (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir (+5-5)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptosi.mir (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fract.f64.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-frame-index.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fshr.mir (+5-5)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-i1-copy.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.mir (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s16.mir (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s64.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert-vector-elt.mir (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-intrinsic-trunc.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-intrinsic-trunc.s16.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-flat.mir (+5-5)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-global.mir (+7-7)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-local.mir (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-constant.mir (+5-5)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global-saddr.mir (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.mir (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.s96.mir (+7-7)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local-128.mir (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local.mir (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-private.mir (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.mir (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.s16.mir (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.v2s16.mir (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-mad_64_32.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-mul.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-add3.mir (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-and-or.mir (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-or3.mir (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.s16.mir (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.s16.mir (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-xor3.mir (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pseudo-scalar-transcendental.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptr-add.mir (+7-7)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptrmask.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptrtoint.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-returnaddress.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sbfx.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-float-sop1.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-float-sop2.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-float-sopc.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-packed.xfail.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-select.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext-inreg.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.mir (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mir (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.v2s16.mir (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smax.mir (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin.mir (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smulh.mir (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-stacksave-stackrestore.invalid.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-stacksave-stackrestore.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-atomic-flat.mir (+5-5)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-atomic-local.mir (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-flat.mir (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.mir (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.s96.mir (+7-7)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-local.mir (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-private.mir (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sub.mir (+5-5)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.v2s16.mir (+5-5)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uadde.gfx10.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uadde.mir (+5-5)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uaddo.mir (+5-5)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ubfx.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uitofp.mir (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umax.mir (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umin.mir (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umulh.mir (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usube.gfx10.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usube.mir (+5-5)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usubo.mir (+5-5)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-sendmsg.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constrained-fp.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fast-math-flags.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.v2i65.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-invariant.ll (+1-1)
``````````diff
diff --git a/llvm/test/CodeGen/AMDGPU/32-bit-local-address-space.ll b/llvm/test/CodeGen/AMDGPU/32-bit-local-address-space.ll
index bf364345c3d089..f257e87dba22e8 100644
--- a/llvm/test/CodeGen/AMDGPU/32-bit-local-address-space.ll
+++ b/llvm/test/CodeGen/AMDGPU/32-bit-local-address-space.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefixes=SI,FUNC,GFX7 %s
-; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=SI,FUNC,GFX8 %s
+; RUN: llc -mtriple=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefixes=SI,FUNC,GFX7 %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=SI,FUNC,GFX8 %s
; On Southern Islands GPUs the local address space(3) uses 32-bit pointers and
; the global address space(1) uses 64-bit pointers. These tests check to make sure
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/addo.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/addo.ll
index a1013f3803e781..ff5880819020da 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/addo.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/addo.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX7 %s
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx801 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX8 %s
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX7 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx801 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX8 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9 %s
define i32 @v_uaddo_i32(i32 %a, i32 %b) {
; GFX7-LABEL: v_uaddo_i32:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll
index b850c37c4a2810..94874a99f93ab3 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX11 %s
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX12 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX11 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX12 %s
define amdgpu_kernel void @s_add_u64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
; GFX11-LABEL: s_add_u64:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll
index 5c451bffc22786..00c3bf30671e07 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=amdgcn -mcpu=fiji -O0 -stop-after=irtranslator -global-isel %s -o - 2>&1 | FileCheck %s
+; RUN: llc -mtriple=amdgcn -mcpu=fiji -O0 -stop-after=irtranslator -global-isel %s -o - 2>&1 | FileCheck %s
; This file checks that the translation from llvm IR to generic
; MachineInstr is correct.
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-prelegalizer-combiner-crash.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-prelegalizer-combiner-crash.mir
index 7c50071e77da53..00050157e97990 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-prelegalizer-combiner-crash.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-prelegalizer-combiner-crash.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
-# RUN: llc -march=amdgcn -mcpu=gfx1030 -run-pass amdgpu-prelegalizer-combiner %s -o - | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -run-pass amdgpu-prelegalizer-combiner %s -o - | FileCheck -check-prefix=GCN %s
---
name: non_inlineable_imm_splat
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll
index aeb6d7d9dc714c..bb5ccc3657dc4d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,WAVE64 %s
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1031 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,WAVE32 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,WAVE64 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1031 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,WAVE32 %s
; End to end tests for scalar vs. vector boolean legalization strategies.
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-no-rtn.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-no-rtn.ll
index 7e6ebd7d91ab57..684fd8a86a6949 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-no-rtn.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-no-rtn.ll
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx908 -verify-machineinstrs -stop-after=instruction-select < %s | FileCheck -check-prefix=GFX908_GFX11 %s
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx90a -verify-machineinstrs -stop-after=instruction-select < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx940 -verify-machineinstrs -stop-after=instruction-select < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs -stop-after=instruction-select < %s | FileCheck -check-prefix=GFX908_GFX11 %s
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1200 -verify-machineinstrs -stop-after=instruction-select < %s | FileCheck -check-prefix=GFX12 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx908 -verify-machineinstrs -stop-after=instruction-select < %s | FileCheck -check-prefix=GFX908_GFX11 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs -stop-after=instruction-select < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx940 -verify-machineinstrs -stop-after=instruction-select < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs -stop-after=instruction-select < %s | FileCheck -check-prefix=GFX908_GFX11 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs -stop-after=instruction-select < %s | FileCheck -check-prefix=GFX12 %s
define amdgpu_ps void @buffer_atomic_fadd_f32_offset_no_rtn(float %val, <4 x i32> inreg %rsrc, i32 inreg %soffset) {
; GFX908_GFX11-LABEL: name: buffer_atomic_fadd_f32_offset_no_rtn
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-rtn.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-rtn.ll
index 4dc7ee21aa21f4..42d4d21f310810 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-rtn.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-rtn.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx90a -verify-machineinstrs -stop-after=instruction-select < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx940 -verify-machineinstrs -stop-after=instruction-select < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs -stop-after=instruction-select < %s | FileCheck -check-prefix=GFX11 %s
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1200 -verify-machineinstrs -stop-after=instruction-select < %s | FileCheck -check-prefix=GFX12 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs -stop-after=instruction-select < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx940 -verify-machineinstrs -stop-after=instruction-select < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs -stop-after=instruction-select < %s | FileCheck -check-prefix=GFX11 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs -stop-after=instruction-select < %s | FileCheck -check-prefix=GFX12 %s
define amdgpu_ps float @buffer_atomic_fadd_f32_offset_rtn(float %val, <4 x i32> inreg %rsrc, i32 inreg %soffset) {
; GFX90A_GFX940-LABEL: name: buffer_atomic_fadd_f32_offset_rtn
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f64.ll
index 910eb9685ab6a9..7c4069b4b3138a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f64.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx90a -verify-machineinstrs -stop-after=instruction-select < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx940 -verify-machineinstrs -stop-after=instruction-select < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs -stop-after=instruction-select < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx940 -verify-machineinstrs -stop-after=instruction-select < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
define amdgpu_ps void @buffer_atomic_fadd_f64_offset_no_rtn(double %val, <4 x i32> inreg %rsrc, i32 inreg %soffset) {
; GFX90A_GFX940-LABEL: name: buffer_atomic_fadd_f64_offset_no_rtn
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-no-rtn.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-no-rtn.ll
index 6a4a0e2d706c99..1ba27c72803d30 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-no-rtn.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-no-rtn.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx908 -verify-machineinstrs -stop-after=instruction-select < %s | FileCheck -check-prefix=GFX908 %s
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx90a -verify-machineinstrs -stop-after=instruction-select < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx940 -verify-machineinstrs -stop-after=instruction-select < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx908 -verify-machineinstrs -stop-after=instruction-select < %s | FileCheck -check-prefix=GFX908 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs -stop-after=instruction-select < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx940 -verify-machineinstrs -stop-after=instruction-select < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
define amdgpu_ps void @buffer_atomic_fadd_v2f16_offset_no_rtn(<2 x half> %val, <4 x i32> inreg %rsrc, i32 inreg %soffset) {
; GFX908-LABEL: name: buffer_atomic_fadd_v2f16_offset_no_rtn
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-rtn.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-rtn.ll
index 8db8ff8a5da768..632ad55fdf892a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-rtn.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-rtn.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx90a -verify-machineinstrs -stop-after=instruction-select < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx940 -verify-machineinstrs -stop-after=instruction-select < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs -stop-after=instruction-select < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx940 -verify-machineinstrs -stop-after=instruction-select < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
define amdgpu_ps <2 x half> @buffer_atomic_fadd_v2f16_offset_rtn(<2 x half> %val, <4 x i32> inreg %rsrc, i32 inreg %soffset) {
; GFX90A_GFX940-LABEL: name: buffer_atomic_fadd_v2f16_offset_rtn
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fabs-fneg.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fabs-fneg.mir
index ed5a190902df69..829d994a922971 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fabs-fneg.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fabs-fneg.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=amdgcn -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
---
name: test_f16
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-fma.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-fma.ll
index cc459814e62ca6..b9846a6a555dce 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-fma.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-fma.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX9-DENORM %s
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -fp-contract=fast < %s | FileCheck -check-prefix=GFX10-CONTRACT %s
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX10-DENORM %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX9-DENORM %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 -fp-contract=fast < %s | FileCheck -check-prefix=GFX10-CONTRACT %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX10-DENORM %s
; fold (fadd (fma x, y, (fpext (fmul u, v))), z) -> (fma x, y, (fma (fpext u), (fpext v), z))
define amdgpu_vs float @test_f16_f32_add_fma_ext_mul(float %x, float %y, float %z, half %u, half %v) {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-mul.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-mul.ll
index f3e56157836396..4ebe1c499a1769 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-mul.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-mul.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX9-FAST-DENORM %s
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX10-FAST-DENORM %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX9-FAST-DENORM %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX10-FAST-DENORM %s
; fold (fadd fast (fpext (fmul fast x, y)), z) -> (fma (fpext x), (fpext y), z)
; fold (fadd fast x, (fpext (fmul fast y, z))) -> (fma (fpext y), (fpext z), x)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll
index 3c9fae3efc30b1..362e25fa932fc0 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -fp-contract=fast < %s | FileCheck -check-prefix=GFX9-CONTRACT %s
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX9-DENORM %s
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -fp-contract=fast < %s | FileCheck -check-prefix=GFX10-CONTRACT %s
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX10-DENORM %s
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1100 -fp-contract=fast < %s | FileCheck -check-prefix=GFX11-CONTRACT %s
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1100 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX11-DENORM %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 -fp-contract=fast < %s | FileCheck -check-prefix=GFX9-CONTRACT %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX9-DENORM %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 -fp-contract=fast < %s | FileCheck -check-prefix=GFX10-CONTRACT %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX10-DENORM %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -fp-contract=fast < %s | FileCheck -check-prefix=GFX11-CONTRACT %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX11-DENORM %s
; fadd (fma a, b, (fmul c, d)), e --> fma a, b, (fma c, d, e)
; fadd e, (fma a, b, (fmul c, d)) --> fma a, b, (fma c, d, e)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul-post-legalize.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul-post-legalize.mir
index 44ca80f75fdb41..dbc0794d3e35b0 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul-post-legalize.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul-post-legalize.mir
@@ -1,12 +1,12 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -run-pass=amdgpu-postlegalizer-combiner %s -o - | FileCheck -check-prefix=GFX9 %s
-# RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -run-pass=amdgpu-postlegalizer-combiner -fp-contract=fast %s -o - | FileCheck -check-prefix=GFX9-CONTRACT %s
-# RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -run-pass=amdgpu-postlegalizer-combiner --denormal-fp-math=preserve-sign %s -o - | FileCheck -check-prefix=GFX9-DENORM %s
-# RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -run-pass=amdgpu-postlegalizer-combiner -enable-unsafe-fp-math %s -o - | FileCheck -check-prefix=GFX9-UNSAFE %s
-# RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -run-pass=amdgpu-postlegalizer-combiner %s -o - | FileCheck -check-prefix=GFX10 %s
-# RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -run-pass=amdgpu-postlegalizer-combiner -fp-contract=fast %s -o - | FileCheck -check-prefix=GFX10-CONTRACT %s
-# RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -run-pass=amdgpu-postlegalizer-combiner --denormal-fp-math=preserve-sign %s -o - | FileCheck -check-prefix=GFX10-DENORM %s
-# RUN: llc -global-isel -march=amdgcn ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/75982
More information about the llvm-commits
mailing list