[llvm] [RISCV] Make Zhinx and Zvfh imply Zhinxmin and Zvfhmin respectively (PR #75735)

Brandon Wu via llvm-commits llvm-commits at lists.llvm.org
Sun Dec 17 19:18:20 PST 2023

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https://github.com/4vtomat approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/75735

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