[llvm] dbe9a60 - [RISCV] Correct the VLOperand for masked vssrl/vssra intrinsics.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-12-17T17:42:08-08:00
New Revision: dbe9a602561d5eecfc1652aab7e127754cb963c0

URL: https://github.com/llvm/llvm-project/commit/dbe9a602561d5eecfc1652aab7e127754cb963c0
DIFF: https://github.com/llvm/llvm-project/commit/dbe9a602561d5eecfc1652aab7e127754cb963c0.diff

LOG: [RISCV] Correct the VLOperand for masked vssrl/vssra intrinsics.

Though I can't prove it matters for anything. The only use of
VLOperand I know of is for handling i64 splat operands to .vx
intrinsics on RV32. Shifts are special and always use XLen for .vx
so they are always legal.

Added: 
    

Modified: 
    llvm/include/llvm/IR/IntrinsicsRISCV.td

Removed: 
    


################################################################################
diff  --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td
index fc830fca392fc5..a391bc53cdb0e9 100644
--- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -702,7 +702,7 @@ let TargetPrefix = "riscv" in {
                      LLVMMatchType<2>, LLVMMatchType<2>],
                     [ImmArg<ArgIndex<4>>,ImmArg<ArgIndex<6>>, IntrNoMem, IntrHasSideEffects]>,
                     RISCVVIntrinsic {
-    let VLOperand = 6;
+    let VLOperand = 5;
   }
   // For Saturating binary operations.
   // The destination vector type is NOT the same as first source vector.