[llvm] [RISCV] Replace RISCVISD::VP_MERGE_VL with a new node that has a separate passthru operand. (PR #75682)

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git-clang-format --diff 433498ce4619d0269977ad6dd273c584301d546f e5bda0a2f0bf0a4449f3391a09b5ea453c4c56fc -- llvm/lib/Target/RISCV/RISCVISelLowering.cpp llvm/lib/Target/RISCV/RISCVISelLowering.h
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 7a9cab0aeb..61d255de3f 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -8231,8 +8231,8 @@ static SDValue lowerVectorIntrinsicScalars(SDValue Op, SelectionDAG &DAG,
                          AVL);
     // TUMA or TUMU: Currently we always emit tumu policy regardless of tuma.
     // It's fine because vmerge does not care mask policy.
-    return DAG.getNode(RISCVISD::VMERGE_VL, DL, VT, Mask, Vec,
-                       MaskedOff, MaskedOff, AVL);
+    return DAG.getNode(RISCVISD::VMERGE_VL, DL, VT, Mask, Vec, MaskedOff,
+                       MaskedOff, AVL);
   }
   }
 
@@ -10312,7 +10312,8 @@ SDValue RISCVTargetLowering::lowerVPOp(SDValue Op, SelectionDAG &DAG) const {
       if (MaskIdx) {
         if (*MaskIdx == OpIdx.index())
           Ops.push_back(DAG.getUNDEF(ContainerVT));
-      } else if (ISD::getVPExplicitVectorLengthIdx(Op.getOpcode()) == OpIdx.index()) {
+      } else if (ISD::getVPExplicitVectorLengthIdx(Op.getOpcode()) ==
+                 OpIdx.index()) {
         // For VP_MERGE, copy the false operand instead of an undef value.
         assert(Op.getOpcode() == ISD::VP_MERGE);
         Ops.push_back(Ops.back());

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https://github.com/llvm/llvm-project/pull/75682