[llvm] 4fa9697 - [RISCV][InsertVSETVLI] Factor out isNonZeroLoadImmediate helper [nfc]

[Philip Reames via llvm-commits]

Author: Philip Reames
Date: 2023-12-15T11:20:01-08:00
New Revision: 4fa9697b478cccc6930a667acfc0d77995b8c263

URL: https://github.com/llvm/llvm-project/commit/4fa9697b478cccc6930a667acfc0d77995b8c263
DIFF: https://github.com/llvm/llvm-project/commit/4fa9697b478cccc6930a667acfc0d77995b8c263.diff

LOG: [RISCV][InsertVSETVLI] Factor out isNonZeroLoadImmediate helper [nfc]

Just reducing a bit of code duplication.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index b2d36b362b3a0f..3400b24e0abb01 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -149,6 +149,13 @@ static std::optional<unsigned> getEEWForLoadStore(const MachineInstr &MI) {
   }
 }
 
+static bool isNonZeroLoadImmediate(MachineInstr &MI) {
+  return MI.getOpcode() == RISCV::ADDI &&
+    MI.getOperand(1).isReg() && MI.getOperand(2).isImm() &&
+    MI.getOperand(1).getReg() == RISCV::X0 &&
+    MI.getOperand(2).getImm() != 0;
+}
+
 /// Return true if this is an operation on mask registers.  Note that
 /// this includes both arithmetic/logical ops and load/store (vlm/vsm).
 static bool isMaskRegOp(const MachineInstr &MI) {
@@ -501,10 +508,7 @@ class VSETVLIInfo {
       if (getAVLReg() == RISCV::X0)
         return true;
       if (MachineInstr *MI = MRI.getVRegDef(getAVLReg());
-          MI && MI->getOpcode() == RISCV::ADDI &&
-          MI->getOperand(1).isReg() && MI->getOperand(2).isImm() &&
-          MI->getOperand(1).getReg() == RISCV::X0 &&
-          MI->getOperand(2).getImm() != 0)
+          MI && isNonZeroLoadImmediate(*MI))
         return true;
       return false;
     }
@@ -1461,10 +1465,7 @@ static bool isNonZeroAVL(const MachineOperand &MO,
     if (MO.getReg() == RISCV::X0)
       return true;
     if (MachineInstr *MI = MRI.getVRegDef(MO.getReg());
-        MI && MI->getOpcode() == RISCV::ADDI &&
-        MI->getOperand(1).isReg() && MI->getOperand(2).isImm() &&
-        MI->getOperand(1).getReg() == RISCV::X0 &&
-        MI->getOperand(2).getImm() != 0)
+        MI && isNonZeroLoadImmediate(*MI))
       return true;
     return false;
   }