[llvm] [RISCV][GlobalISel] Represent RISC-V vector types using LLT scalable vectors; and legalize vectorized operations for G_ADD, G_SUB, G_AND, G_OR, and G_XOR opcodes (PR #71400)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Dec 15 09:59:07 PST 2023
https://github.com/topperc approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/71400
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