[llvm] [LLVM][AArch64][tblgen]: Match clamp pattern (PR #75529)

[Paul Walker via llvm-commits]

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@@ -4054,10 +4050,36 @@ defm BFMAXNM_ZPZZ : sve2p1_bf_bin_pred_zds<AArch64fmaxnm_p>;
 defm BFMINNM_ZPZZ : sve2p1_bf_bin_pred_zds<AArch64fminnm_p>;
 
 defm BFMUL_ZZZI : sve2p1_fp_bfmul_by_indexed_elem<"bfmul", int_aarch64_sve_fmul_lane>;
-
-defm BFCLAMP_ZZZ : sve2p1_bfclamp<"bfclamp", int_aarch64_sve_fclamp>;
 } // End HasSVE2p1_or_HasSME2p1, HasB16B16
 
+// Replace pattern min(max(v1,v2),v3) by clamp
+def clamp_min_max : PatFrags<(ops node:$Zd, node:$Zn, node:$Zm),
+                              [(AArch64smin_p (SVEAllActive),
+                                  (AArch64smax_p (SVEAllActive), node:$Zd, node:$Zn),
+                                  node:$Zm),
+                              (AArch64fmin_p (SVEAllActive),
+                                  (AArch64fmax_p (SVEAllActive), node:$Zd, node:$Zn),
+                                  node:$Zm)
+                               ]>;
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paulwalker-arm wrote:

This is not the intended rational for using PatFrags.  The goal is to combine multiple patterns that correspond to the same operation so that you can have a single isel pattern per instruction.

This means that rather than grouping signed-integer and floating-point operations which whilst similar are not the same operation you instead create a PatFrags for `sclamp`[1] that has the intrinsic and the `smin(zmax())` patterns. You'll see we put all the PatFrags at the top of this file.

Doing this means you will not need to move the `SCLAMP_ZZZ : sve2_clamp...` code, just replace the passed in op (i.e. replace `int_aarch64_sve_fclamp` with `sclamp`.

[1] For the SVE instruction we try to name the PatFrag after the instruction only, plus a predicated suffix when relevant, which it isn't in this case.

https://github.com/llvm/llvm-project/pull/75529