[llvm] [X86][MC] Support Enc/Dec for EGPR for promoted SHA instruction (PR #75582)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Dec 15 02:05:30 PST 2023
https://github.com/XinWang10 created https://github.com/llvm/llvm-project/pull/75582
R16-R31 was added into GPRs in https://github.com/llvm/llvm-project/pull/70958,
This patch supports the encoding/decoding for promoted SHA instruction in EVEX space.
RFC: https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4
>From 452f812dedbfb8f417a61b07f88a66785398171c Mon Sep 17 00:00:00 2001
From: "Wang, Xin10" <xin10.wang at intel.com>
Date: Fri, 15 Dec 2023 02:01:12 -0800
Subject: [PATCH] [X86][MC] Support Enc/Dec for EGPR for promoted SHA
instruction
---
llvm/lib/Target/X86/X86InstrSSE.td | 95 ++++++++++++++-----
.../test/MC/Disassembler/X86/apx/sha1msg1.txt | 10 ++
.../test/MC/Disassembler/X86/apx/sha1msg2.txt | 10 ++
.../MC/Disassembler/X86/apx/sha1nexte.txt | 10 ++
.../MC/Disassembler/X86/apx/sha1rnds4.txt | 10 ++
.../MC/Disassembler/X86/apx/sha256msg1.txt | 10 ++
.../MC/Disassembler/X86/apx/sha256msg2.txt | 10 ++
.../MC/Disassembler/X86/apx/sha256rnds2.txt | 10 ++
llvm/test/MC/X86/apx/sha1msg1-att.s | 9 ++
llvm/test/MC/X86/apx/sha1msg1-intel.s | 10 ++
llvm/test/MC/X86/apx/sha1msg2-att.s | 9 ++
llvm/test/MC/X86/apx/sha1msg2-intel.s | 9 ++
llvm/test/MC/X86/apx/sha1nexte-att.s | 9 ++
llvm/test/MC/X86/apx/sha1nexte-intel.s | 9 ++
llvm/test/MC/X86/apx/sha1rnds4-att.s | 9 ++
llvm/test/MC/X86/apx/sha1rnds4-intel.s | 9 ++
llvm/test/MC/X86/apx/sha256msg1-att.s | 9 ++
llvm/test/MC/X86/apx/sha256msg1-intel.s | 9 ++
llvm/test/MC/X86/apx/sha256msg2-att.s | 9 ++
llvm/test/MC/X86/apx/sha256msg2-intel.s | 9 ++
llvm/test/MC/X86/apx/sha256rnds2-att.s | 9 ++
llvm/test/MC/X86/apx/sha256rnds2-intel.s | 10 ++
llvm/test/TableGen/x86-fold-tables.inc | 7 ++
23 files changed, 276 insertions(+), 24 deletions(-)
create mode 100644 llvm/test/MC/Disassembler/X86/apx/sha1msg1.txt
create mode 100644 llvm/test/MC/Disassembler/X86/apx/sha1msg2.txt
create mode 100644 llvm/test/MC/Disassembler/X86/apx/sha1nexte.txt
create mode 100644 llvm/test/MC/Disassembler/X86/apx/sha1rnds4.txt
create mode 100644 llvm/test/MC/Disassembler/X86/apx/sha256msg1.txt
create mode 100644 llvm/test/MC/Disassembler/X86/apx/sha256msg2.txt
create mode 100644 llvm/test/MC/Disassembler/X86/apx/sha256rnds2.txt
create mode 100644 llvm/test/MC/X86/apx/sha1msg1-att.s
create mode 100644 llvm/test/MC/X86/apx/sha1msg1-intel.s
create mode 100644 llvm/test/MC/X86/apx/sha1msg2-att.s
create mode 100644 llvm/test/MC/X86/apx/sha1msg2-intel.s
create mode 100644 llvm/test/MC/X86/apx/sha1nexte-att.s
create mode 100644 llvm/test/MC/X86/apx/sha1nexte-intel.s
create mode 100644 llvm/test/MC/X86/apx/sha1rnds4-att.s
create mode 100644 llvm/test/MC/X86/apx/sha1rnds4-intel.s
create mode 100644 llvm/test/MC/X86/apx/sha256msg1-att.s
create mode 100644 llvm/test/MC/X86/apx/sha256msg1-intel.s
create mode 100644 llvm/test/MC/X86/apx/sha256msg2-att.s
create mode 100644 llvm/test/MC/X86/apx/sha256msg2-intel.s
create mode 100644 llvm/test/MC/X86/apx/sha256rnds2-att.s
create mode 100644 llvm/test/MC/X86/apx/sha256rnds2-intel.s
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td
index cf57fe562ed5c4..acf068d38b5de9 100644
--- a/llvm/lib/Target/X86/X86InstrSSE.td
+++ b/llvm/lib/Target/X86/X86InstrSSE.td
@@ -6706,31 +6706,31 @@ let Constraints = "$src1 = $dst" in {
// FIXME: Is there a better scheduler class for SHA than WriteVecIMul?
multiclass SHAI_binop<bits<8> Opc, string OpcodeStr, Intrinsic IntId,
- X86FoldableSchedWrite sched, bit UsesXMM0 = 0> {
- def rr : I<Opc, MRMSrcReg, (outs VR128:$dst),
- (ins VR128:$src1, VR128:$src2),
- !if(UsesXMM0,
- !strconcat(OpcodeStr, "\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}"),
- !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}")),
- [!if(UsesXMM0,
- (set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0)),
- (set VR128:$dst, (IntId VR128:$src1, VR128:$src2)))]>,
- T8PS, Sched<[sched]>;
-
- def rm : I<Opc, MRMSrcMem, (outs VR128:$dst),
- (ins VR128:$src1, i128mem:$src2),
- !if(UsesXMM0,
- !strconcat(OpcodeStr, "\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}"),
- !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}")),
- [!if(UsesXMM0,
- (set VR128:$dst, (IntId VR128:$src1,
- (memop addr:$src2), XMM0)),
- (set VR128:$dst, (IntId VR128:$src1,
- (memop addr:$src2))))]>, T8PS,
- Sched<[sched.Folded, sched.ReadAfterFold]>;
+ X86FoldableSchedWrite sched, string Suffix = "", bit UsesXMM0 = 0> {
+ def rr#Suffix : I<Opc, MRMSrcReg, (outs VR128:$dst),
+ (ins VR128:$src1, VR128:$src2),
+ !if(UsesXMM0,
+ !strconcat(OpcodeStr, "\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}"),
+ !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}")),
+ [!if(UsesXMM0,
+ (set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0)),
+ (set VR128:$dst, (IntId VR128:$src1, VR128:$src2)))]>,
+ T8PS, Sched<[sched]>;
+
+ def rm#Suffix : I<Opc, MRMSrcMem, (outs VR128:$dst),
+ (ins VR128:$src1, i128mem:$src2),
+ !if(UsesXMM0,
+ !strconcat(OpcodeStr, "\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}"),
+ !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}")),
+ [!if(UsesXMM0,
+ (set VR128:$dst, (IntId VR128:$src1,
+ (memop addr:$src2), XMM0)),
+ (set VR128:$dst, (IntId VR128:$src1,
+ (memop addr:$src2))))]>, T8PS,
+ Sched<[sched.Folded, sched.ReadAfterFold]>;
}
-let Constraints = "$src1 = $dst", Predicates = [HasSHA] in {
+let Constraints = "$src1 = $dst", Predicates = [HasSHA, NoEGPR] in {
def SHA1RNDS4rri : Ii8<0xCC, MRMSrcReg, (outs VR128:$dst),
(ins VR128:$src1, VR128:$src2, u8imm:$src3),
"sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
@@ -6757,7 +6757,7 @@ let Constraints = "$src1 = $dst", Predicates = [HasSHA] in {
let Uses=[XMM0] in
defm SHA256RNDS2 : SHAI_binop<0xCB, "sha256rnds2", int_x86_sha256rnds2,
- SchedWriteVecIMul.XMM, 1>;
+ SchedWriteVecIMul.XMM, "", 1>;
defm SHA256MSG1 : SHAI_binop<0xCC, "sha256msg1", int_x86_sha256msg1,
SchedWriteVecIMul.XMM>;
@@ -6765,12 +6765,59 @@ let Constraints = "$src1 = $dst", Predicates = [HasSHA] in {
SchedWriteVecIMul.XMM>;
}
+let Constraints = "$src1 = $dst", Predicates = [HasSHA, HasEGPR, In64BitMode]in {
+ def SHA1RNDS4rri_EVEX: Ii8<0xD4, MRMSrcReg, (outs VR128:$dst),
+ (ins VR128:$src1, VR128:$src2, u8imm:$src3),
+ "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
+ [(set VR128:$dst,
+ (int_x86_sha1rnds4 VR128:$src1, VR128:$src2,
+ (i8 timm:$src3)))]>,
+ EVEX_NoCD8, T_MAP4PS, Sched<[SchedWriteVecIMul.XMM]>;
+ def SHA1RNDS4rmi_EVEX: Ii8<0xD4, MRMSrcMem, (outs VR128:$dst),
+ (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
+ "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
+ [(set VR128:$dst,
+ (int_x86_sha1rnds4 VR128:$src1,
+ (memop addr:$src2),
+ (i8 timm:$src3)))]>,
+ EVEX_NoCD8, T_MAP4PS,
+ Sched<[SchedWriteVecIMul.XMM.Folded,
+ SchedWriteVecIMul.XMM.ReadAfterFold]>;
+
+ defm SHA1NEXTE : SHAI_binop<0xD8, "sha1nexte", int_x86_sha1nexte,
+ SchedWriteVecIMul.XMM, "_EVEX">,
+ EVEX_NoCD8, T_MAP4PS;
+ defm SHA1MSG1 : SHAI_binop<0xD9, "sha1msg1", int_x86_sha1msg1,
+ SchedWriteVecIMul.XMM, "_EVEX">,
+ EVEX_NoCD8, T_MAP4PS;
+ defm SHA1MSG2 : SHAI_binop<0xDA, "sha1msg2", int_x86_sha1msg2,
+ SchedWriteVecIMul.XMM, "_EVEX">,
+ EVEX_NoCD8, T_MAP4PS;
+
+ let Uses=[XMM0] in
+ defm SHA256RNDS2 : SHAI_binop<0xDB, "sha256rnds2", int_x86_sha256rnds2,
+ SchedWriteVecIMul.XMM, "_EVEX", 1>,
+ EVEX_NoCD8, T_MAP4PS;
+
+ defm SHA256MSG1 : SHAI_binop<0xDC, "sha256msg1", int_x86_sha256msg1,
+ SchedWriteVecIMul.XMM, "_EVEX">,
+ EVEX_NoCD8, T_MAP4PS;
+ defm SHA256MSG2 : SHAI_binop<0xDD, "sha256msg2", int_x86_sha256msg2,
+ SchedWriteVecIMul.XMM, "_EVEX">,
+ EVEX_NoCD8, T_MAP4PS;
+}
+
// Aliases with explicit %xmm0
def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}",
(SHA256RNDS2rr VR128:$dst, VR128:$src2), 0>;
def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}",
(SHA256RNDS2rm VR128:$dst, i128mem:$src2), 0>;
+def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}",
+ (SHA256RNDS2rr_EVEX VR128:$dst, VR128:$src2), 0>;
+def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}",
+ (SHA256RNDS2rm_EVEX VR128:$dst, i128mem:$src2), 0>;
+
//===----------------------------------------------------------------------===//
// AES-NI Instructions
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/MC/Disassembler/X86/apx/sha1msg1.txt b/llvm/test/MC/Disassembler/X86/apx/sha1msg1.txt
new file mode 100644
index 00000000000000..1c94fa88a3d3cf
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/sha1msg1.txt
@@ -0,0 +1,10 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT: sha1msg1 %xmm13, %xmm12
+# INTEL: sha1msg1 xmm12, xmm13
+0x45,0x0f,0x38,0xc9,0xe5
+
+# ATT: sha1msg1 291(%r28,%r29,4), %xmm12
+# INTEL: sha1msg1 xmm12, xmmword ptr [r28 + 4*r29 + 291]
+0x62,0x1c,0x78,0x08,0xd9,0xa4,0xac,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/X86/apx/sha1msg2.txt b/llvm/test/MC/Disassembler/X86/apx/sha1msg2.txt
new file mode 100644
index 00000000000000..5fd17d9f326006
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/sha1msg2.txt
@@ -0,0 +1,10 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT: sha1msg2 %xmm13, %xmm12
+# INTEL: sha1msg2 xmm12, xmm13
+0x45,0x0f,0x38,0xca,0xe5
+
+# ATT: sha1msg2 291(%r28,%r29,4), %xmm12
+# INTEL: sha1msg2 xmm12, xmmword ptr [r28 + 4*r29 + 291]
+0x62,0x1c,0x78,0x08,0xda,0xa4,0xac,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/X86/apx/sha1nexte.txt b/llvm/test/MC/Disassembler/X86/apx/sha1nexte.txt
new file mode 100644
index 00000000000000..3c5eae3d7177fc
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/sha1nexte.txt
@@ -0,0 +1,10 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT: sha1nexte %xmm13, %xmm12
+# INTEL: sha1nexte xmm12, xmm13
+0x45,0x0f,0x38,0xc8,0xe5
+
+# ATT: sha1nexte 291(%r28,%r29,4), %xmm12
+# INTEL: sha1nexte xmm12, xmmword ptr [r28 + 4*r29 + 291]
+0x62,0x1c,0x78,0x08,0xd8,0xa4,0xac,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/X86/apx/sha1rnds4.txt b/llvm/test/MC/Disassembler/X86/apx/sha1rnds4.txt
new file mode 100644
index 00000000000000..a05f17739606ac
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/sha1rnds4.txt
@@ -0,0 +1,10 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT: sha1rnds4 $123, %xmm13, %xmm12
+# INTEL: sha1rnds4 xmm12, xmm13, 123
+0x45,0x0f,0x3a,0xcc,0xe5,0x7b
+
+# ATT: sha1rnds4 $123, 291(%r28,%r29,4), %xmm12
+# INTEL: sha1rnds4 xmm12, xmmword ptr [r28 + 4*r29 + 291], 123
+0x62,0x1c,0x78,0x08,0xd4,0xa4,0xac,0x23,0x01,0x00,0x00,0x7b
diff --git a/llvm/test/MC/Disassembler/X86/apx/sha256msg1.txt b/llvm/test/MC/Disassembler/X86/apx/sha256msg1.txt
new file mode 100644
index 00000000000000..b4c14866647dd6
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/sha256msg1.txt
@@ -0,0 +1,10 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT: sha256msg1 %xmm13, %xmm12
+# INTEL: sha256msg1 xmm12, xmm13
+0x45,0x0f,0x38,0xcc,0xe5
+
+# ATT: sha256msg1 291(%r28,%r29,4), %xmm12
+# INTEL: sha256msg1 xmm12, xmmword ptr [r28 + 4*r29 + 291]
+0x62,0x1c,0x78,0x08,0xdc,0xa4,0xac,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/X86/apx/sha256msg2.txt b/llvm/test/MC/Disassembler/X86/apx/sha256msg2.txt
new file mode 100644
index 00000000000000..75099b428e2b67
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/sha256msg2.txt
@@ -0,0 +1,10 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT: sha256msg2 %xmm13, %xmm12
+# INTEL: sha256msg2 xmm12, xmm13
+0x45,0x0f,0x38,0xcd,0xe5
+
+# ATT: sha256msg2 291(%r28,%r29,4), %xmm12
+# INTEL: sha256msg2 xmm12, xmmword ptr [r28 + 4*r29 + 291]
+0x62,0x1c,0x78,0x08,0xdd,0xa4,0xac,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/X86/apx/sha256rnds2.txt b/llvm/test/MC/Disassembler/X86/apx/sha256rnds2.txt
new file mode 100644
index 00000000000000..1ca60aa9e9b1a2
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/sha256rnds2.txt
@@ -0,0 +1,10 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT: sha256rnds2 %xmm0, %xmm13, %xmm12
+# INTEL: sha256rnds2 xmm12, xmm13, xmm0
+0x45,0x0f,0x38,0xcb,0xe5
+
+# ATT: sha256rnds2 %xmm0, 291(%r28,%r29,4), %xmm12
+# INTEL: sha256rnds2 xmm12, xmmword ptr [r28 + 4*r29 + 291], xmm0
+0x62,0x1c,0x78,0x08,0xdb,0xa4,0xac,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/X86/apx/sha1msg1-att.s b/llvm/test/MC/X86/apx/sha1msg1-att.s
new file mode 100644
index 00000000000000..900b1b703c48ba
--- /dev/null
+++ b/llvm/test/MC/X86/apx/sha1msg1-att.s
@@ -0,0 +1,9 @@
+# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+
+# CHECK: sha1msg1 %xmm13, %xmm12
+# CHECK: encoding: [0x45,0x0f,0x38,0xc9,0xe5]
+ sha1msg1 %xmm13, %xmm12
+
+# CHECK: sha1msg1 291(%r28,%r29,4), %xmm12
+# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xd9,0xa4,0xac,0x23,0x01,0x00,0x00]
+ sha1msg1 291(%r28,%r29,4), %xmm12
diff --git a/llvm/test/MC/X86/apx/sha1msg1-intel.s b/llvm/test/MC/X86/apx/sha1msg1-intel.s
new file mode 100644
index 00000000000000..bd574633445241
--- /dev/null
+++ b/llvm/test/MC/X86/apx/sha1msg1-intel.s
@@ -0,0 +1,10 @@
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+# CHECK: sha1msg1 xmm12, xmm13
+# CHECK: encoding: [0x45,0x0f,0x38,0xc9,0xe5]
+ sha1msg1 xmm12, xmm13
+
+# CHECK: sha1msg1 xmm12, xmmword ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xd9,0xa4,0xac,0x23,0x01,0x00,0x00]
+ sha1msg1 xmm12, xmmword ptr [r28 + 4*r29 + 291]
+
\ No newline at end of file
diff --git a/llvm/test/MC/X86/apx/sha1msg2-att.s b/llvm/test/MC/X86/apx/sha1msg2-att.s
new file mode 100644
index 00000000000000..62557e46f8b9d0
--- /dev/null
+++ b/llvm/test/MC/X86/apx/sha1msg2-att.s
@@ -0,0 +1,9 @@
+# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+
+# CHECK: sha1msg2 %xmm13, %xmm12
+# CHECK: encoding: [0x45,0x0f,0x38,0xca,0xe5]
+ sha1msg2 %xmm13, %xmm12
+
+# CHECK: sha1msg2 291(%r28,%r29,4), %xmm12
+# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xda,0xa4,0xac,0x23,0x01,0x00,0x00]
+ sha1msg2 291(%r28,%r29,4), %xmm12
diff --git a/llvm/test/MC/X86/apx/sha1msg2-intel.s b/llvm/test/MC/X86/apx/sha1msg2-intel.s
new file mode 100644
index 00000000000000..546a56263bbe20
--- /dev/null
+++ b/llvm/test/MC/X86/apx/sha1msg2-intel.s
@@ -0,0 +1,9 @@
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+# CHECK: sha1msg2 xmm12, xmm13
+# CHECK: encoding: [0x45,0x0f,0x38,0xca,0xe5]
+ sha1msg2 xmm12, xmm13
+
+# CHECK: sha1msg2 xmm12, xmmword ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xda,0xa4,0xac,0x23,0x01,0x00,0x00]
+ sha1msg2 xmm12, xmmword ptr [r28 + 4*r29 + 291]
diff --git a/llvm/test/MC/X86/apx/sha1nexte-att.s b/llvm/test/MC/X86/apx/sha1nexte-att.s
new file mode 100644
index 00000000000000..70e8300cb70a7c
--- /dev/null
+++ b/llvm/test/MC/X86/apx/sha1nexte-att.s
@@ -0,0 +1,9 @@
+# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+
+# CHECK: sha1nexte %xmm13, %xmm12
+# CHECK: encoding: [0x45,0x0f,0x38,0xc8,0xe5]
+ sha1nexte %xmm13, %xmm12
+
+# CHECK: sha1nexte 291(%r28,%r29,4), %xmm12
+# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xd8,0xa4,0xac,0x23,0x01,0x00,0x00]
+ sha1nexte 291(%r28,%r29,4), %xmm12
diff --git a/llvm/test/MC/X86/apx/sha1nexte-intel.s b/llvm/test/MC/X86/apx/sha1nexte-intel.s
new file mode 100644
index 00000000000000..1c890c3cda44ad
--- /dev/null
+++ b/llvm/test/MC/X86/apx/sha1nexte-intel.s
@@ -0,0 +1,9 @@
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+# CHECK: sha1nexte xmm12, xmm13
+# CHECK: encoding: [0x45,0x0f,0x38,0xc8,0xe5]
+ sha1nexte xmm12, xmm13
+
+# CHECK: sha1nexte xmm12, xmmword ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xd8,0xa4,0xac,0x23,0x01,0x00,0x00]
+ sha1nexte xmm12, xmmword ptr [r28 + 4*r29 + 291]
diff --git a/llvm/test/MC/X86/apx/sha1rnds4-att.s b/llvm/test/MC/X86/apx/sha1rnds4-att.s
new file mode 100644
index 00000000000000..1d24c83a0b30e5
--- /dev/null
+++ b/llvm/test/MC/X86/apx/sha1rnds4-att.s
@@ -0,0 +1,9 @@
+# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+
+# CHECK: sha1rnds4 $123, %xmm13, %xmm12
+# CHECK: encoding: [0x45,0x0f,0x3a,0xcc,0xe5,0x7b]
+ sha1rnds4 $123, %xmm13, %xmm12
+
+# CHECK: sha1rnds4 $123, 291(%r28,%r29,4), %xmm12
+# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xd4,0xa4,0xac,0x23,0x01,0x00,0x00,0x7b]
+ sha1rnds4 $123, 291(%r28,%r29,4), %xmm12
diff --git a/llvm/test/MC/X86/apx/sha1rnds4-intel.s b/llvm/test/MC/X86/apx/sha1rnds4-intel.s
new file mode 100644
index 00000000000000..53620856bbf0fc
--- /dev/null
+++ b/llvm/test/MC/X86/apx/sha1rnds4-intel.s
@@ -0,0 +1,9 @@
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+# CHECK: sha1rnds4 xmm12, xmm13, 123
+# CHECK: encoding: [0x45,0x0f,0x3a,0xcc,0xe5,0x7b]
+ sha1rnds4 xmm12, xmm13, 123
+
+# CHECK: sha1rnds4 xmm12, xmmword ptr [r28 + 4*r29 + 291], 123
+# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xd4,0xa4,0xac,0x23,0x01,0x00,0x00,0x7b]
+ sha1rnds4 xmm12, xmmword ptr [r28 + 4*r29 + 291], 123
diff --git a/llvm/test/MC/X86/apx/sha256msg1-att.s b/llvm/test/MC/X86/apx/sha256msg1-att.s
new file mode 100644
index 00000000000000..c6d833dc78039a
--- /dev/null
+++ b/llvm/test/MC/X86/apx/sha256msg1-att.s
@@ -0,0 +1,9 @@
+# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+
+# CHECK: sha256msg1 %xmm13, %xmm12
+# CHECK: encoding: [0x45,0x0f,0x38,0xcc,0xe5]
+ sha256msg1 %xmm13, %xmm12
+
+# CHECK: sha256msg1 291(%r28,%r29,4), %xmm12
+# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xdc,0xa4,0xac,0x23,0x01,0x00,0x00]
+ sha256msg1 291(%r28,%r29,4), %xmm12
diff --git a/llvm/test/MC/X86/apx/sha256msg1-intel.s b/llvm/test/MC/X86/apx/sha256msg1-intel.s
new file mode 100644
index 00000000000000..e3e96f9e2f7d55
--- /dev/null
+++ b/llvm/test/MC/X86/apx/sha256msg1-intel.s
@@ -0,0 +1,9 @@
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+# CHECK: sha256msg1 xmm12, xmm13
+# CHECK: encoding: [0x45,0x0f,0x38,0xcc,0xe5]
+ sha256msg1 xmm12, xmm13
+
+# CHECK: sha256msg1 xmm12, xmmword ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xdc,0xa4,0xac,0x23,0x01,0x00,0x00]
+ sha256msg1 xmm12, xmmword ptr [r28 + 4*r29 + 291]
diff --git a/llvm/test/MC/X86/apx/sha256msg2-att.s b/llvm/test/MC/X86/apx/sha256msg2-att.s
new file mode 100644
index 00000000000000..979ee88633b675
--- /dev/null
+++ b/llvm/test/MC/X86/apx/sha256msg2-att.s
@@ -0,0 +1,9 @@
+# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+
+# CHECK: sha256msg2 %xmm13, %xmm12
+# CHECK: encoding: [0x45,0x0f,0x38,0xcd,0xe5]
+ sha256msg2 %xmm13, %xmm12
+
+# CHECK: sha256msg2 291(%r28,%r29,4), %xmm12
+# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xdd,0xa4,0xac,0x23,0x01,0x00,0x00]
+ sha256msg2 291(%r28,%r29,4), %xmm12
\ No newline at end of file
diff --git a/llvm/test/MC/X86/apx/sha256msg2-intel.s b/llvm/test/MC/X86/apx/sha256msg2-intel.s
new file mode 100644
index 00000000000000..043633de1c0413
--- /dev/null
+++ b/llvm/test/MC/X86/apx/sha256msg2-intel.s
@@ -0,0 +1,9 @@
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+# CHECK: sha256msg2 xmm12, xmm13
+# CHECK: encoding: [0x45,0x0f,0x38,0xcd,0xe5]
+ sha256msg2 xmm12, xmm13
+
+# CHECK: sha256msg2 xmm12, xmmword ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xdd,0xa4,0xac,0x23,0x01,0x00,0x00]
+ sha256msg2 xmm12, xmmword ptr [r28 + 4*r29 + 291]
diff --git a/llvm/test/MC/X86/apx/sha256rnds2-att.s b/llvm/test/MC/X86/apx/sha256rnds2-att.s
new file mode 100644
index 00000000000000..56ae30a2e3a9e9
--- /dev/null
+++ b/llvm/test/MC/X86/apx/sha256rnds2-att.s
@@ -0,0 +1,9 @@
+# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+
+# CHECK: sha256rnds2 %xmm0, %xmm13, %xmm12
+# CHECK: encoding: [0x45,0x0f,0x38,0xcb,0xe5]
+ sha256rnds2 %xmm0, %xmm13, %xmm12
+
+# CHECK: sha256rnds2 %xmm0, 291(%r28,%r29,4), %xmm12
+# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xdb,0xa4,0xac,0x23,0x01,0x00,0x00]
+ sha256rnds2 %xmm0, 291(%r28,%r29,4), %xmm12
diff --git a/llvm/test/MC/X86/apx/sha256rnds2-intel.s b/llvm/test/MC/X86/apx/sha256rnds2-intel.s
new file mode 100644
index 00000000000000..4ae727de80b919
--- /dev/null
+++ b/llvm/test/MC/X86/apx/sha256rnds2-intel.s
@@ -0,0 +1,10 @@
+
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+# CHECK: sha256rnds2 xmm12, xmm13, xmm0
+# CHECK: encoding: [0x45,0x0f,0x38,0xcb,0xe5]
+ sha256rnds2 xmm12, xmm13, xmm0
+
+# CHECK: sha256rnds2 xmm12, xmmword ptr [r28 + 4*r29 + 291], xmm0
+# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xdb,0xa4,0xac,0x23,0x01,0x00,0x00]
+ sha256rnds2 xmm12, xmmword ptr [r28 + 4*r29 + 291], xmm0
diff --git a/llvm/test/TableGen/x86-fold-tables.inc b/llvm/test/TableGen/x86-fold-tables.inc
index 67b5c6cc288911..8d9ca6c39dc4db 100644
--- a/llvm/test/TableGen/x86-fold-tables.inc
+++ b/llvm/test/TableGen/x86-fold-tables.inc
@@ -1632,12 +1632,19 @@ static const X86FoldTableEntry Table2[] = {
{X86::SBB64rr, X86::SBB64rm, 0},
{X86::SBB8rr, X86::SBB8rm, 0},
{X86::SHA1MSG1rr, X86::SHA1MSG1rm, TB_ALIGN_16},
+ {X86::SHA1MSG1rr_EVEX, X86::SHA1MSG1rm_EVEX, 0},
{X86::SHA1MSG2rr, X86::SHA1MSG2rm, TB_ALIGN_16},
+ {X86::SHA1MSG2rr_EVEX, X86::SHA1MSG2rm_EVEX, 0},
{X86::SHA1NEXTErr, X86::SHA1NEXTErm, TB_ALIGN_16},
+ {X86::SHA1NEXTErr_EVEX, X86::SHA1NEXTErm_EVEX, 0},
{X86::SHA1RNDS4rri, X86::SHA1RNDS4rmi, TB_ALIGN_16},
+ {X86::SHA1RNDS4rri_EVEX, X86::SHA1RNDS4rmi_EVEX, 0},
{X86::SHA256MSG1rr, X86::SHA256MSG1rm, TB_ALIGN_16},
+ {X86::SHA256MSG1rr_EVEX, X86::SHA256MSG1rm_EVEX, 0},
{X86::SHA256MSG2rr, X86::SHA256MSG2rm, TB_ALIGN_16},
+ {X86::SHA256MSG2rr_EVEX, X86::SHA256MSG2rm_EVEX, 0},
{X86::SHA256RNDS2rr, X86::SHA256RNDS2rm, TB_ALIGN_16},
+ {X86::SHA256RNDS2rr_EVEX, X86::SHA256RNDS2rm_EVEX, 0},
{X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16},
{X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16},
{X86::SQRTSDr_Int, X86::SQRTSDm_Int, TB_NO_REVERSE},
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