[llvm] [LLVM][AArch64][tblgen]: Match clamp pattern (PR #75529)

[via llvm-commits]

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@@ -4054,10 +4050,36 @@ defm BFMAXNM_ZPZZ : sve2p1_bf_bin_pred_zds<AArch64fmaxnm_p>;
 defm BFMINNM_ZPZZ : sve2p1_bf_bin_pred_zds<AArch64fminnm_p>;
 
 defm BFMUL_ZZZI : sve2p1_fp_bfmul_by_indexed_elem<"bfmul", int_aarch64_sve_fmul_lane>;
-
-defm BFCLAMP_ZZZ : sve2p1_bfclamp<"bfclamp", int_aarch64_sve_fclamp>;
 } // End HasSVE2p1_or_HasSME2p1, HasB16B16
 
+// Replace pattern min(max(v1,v2),v3) by clamp
+def clamp_min_max : PatFrags<(ops node:$Zd, node:$Zn, node:$Zm),
+                              [(AArch64smin_p (SVEAllActive),
+                                  (AArch64smax_p (SVEAllActive), node:$Zd, node:$Zn),
+                                  node:$Zm),
+                              (AArch64fmin_p (SVEAllActive),
+                                  (AArch64fmax_p (SVEAllActive), node:$Zd, node:$Zn),
+                                  node:$Zm)
+                               ]>;
+def uclamp_min_max : PatFrag<(ops node:$Zd, node:$Zn, node:$Zm),
+                              (AArch64umin_p (SVEAllActive),
+                                  (AArch64umax_p (SVEAllActive), node:$Zd, node:$Zn),
+                                  node:$Zm)>;
+def bfclamp_min_max : PatFrag<(ops node:$pg, node:$Zd, node:$Zn, node:$Zm),
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CarolineConcatto wrote:

Should we add the same changes for int_aarch64_sve_fmin and int_aarch64_sve_fmax with nxv4f32 and nxv2f64
And another for int_aarch64_sve_[s,u]min/int_aarch64_sve_[s,u]min?

https://github.com/llvm/llvm-project/pull/75529