[lld] [llvm] Revert "[RISCV] Support printing immediate of RISCV MCInst in hexadecimal format" (PR #75561)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Dec 14 22:04:08 PST 2023
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-lld
Author: Vitaly Buka (vitalybuka)
<details>
<summary>Changes</summary>
Reverts llvm/llvm-project#<!-- -->74053
Breaks https://lab.llvm.org/buildbot/#/builders/5/builds/39291
---
Patch is 176.19 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/75561.diff
136 Files Affected:
- (modified) bolt/test/RISCV/call-annotations.s (+2-2)
- (modified) bolt/test/RISCV/relax.s (+3-3)
- (modified) bolt/test/RISCV/reloc-tls.s (+3-3)
- (modified) bolt/test/RISCV/reorder-blocks-reverse.s (+2-2)
- (modified) bolt/test/RISCV/tls-le-gnu-ld.test (+2-2)
- (modified) lld/test/ELF/riscv-call.s (+8-8)
- (modified) lld/test/ELF/riscv-hi20-lo12.s (+11-11)
- (modified) lld/test/ELF/riscv-ifunc-nonpreemptible.s (+8-8)
- (modified) lld/test/ELF/riscv-pcrel-hilo.s (+12-12)
- (modified) lld/test/ELF/riscv-plt.s (+24-24)
- (modified) lld/test/ELF/riscv-relax-align-rvc.s (+31-31)
- (modified) lld/test/ELF/riscv-relax-align.s (+63-63)
- (modified) lld/test/ELF/riscv-relax-call.s (+23-23)
- (modified) lld/test/ELF/riscv-relax-call2.s (+6-6)
- (modified) lld/test/ELF/riscv-relax-emit-relocs.s (+12-12)
- (modified) lld/test/ELF/riscv-relax-hi20-lo12-pie.s (+4-4)
- (modified) lld/test/ELF/riscv-relax-hi20-lo12.s (+11-11)
- (modified) lld/test/ELF/riscv-reloc-got.s (+8-8)
- (modified) lld/test/ELF/riscv-tls-gd.s (+16-16)
- (modified) lld/test/ELF/riscv-tls-ie.s (+14-14)
- (modified) lld/test/ELF/riscv-tls-ld.s (+14-14)
- (modified) lld/test/ELF/riscv-tls-le.s (+19-19)
- (modified) lld/test/ELF/riscv-undefined-weak.s (+11-11)
- (modified) llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp (+4-4)
- (modified) llvm/test/CodeGen/RISCV/compress-double.ll (+1-1)
- (modified) llvm/test/CodeGen/RISCV/compress-float.ll (+1-1)
- (modified) llvm/test/CodeGen/RISCV/compress-opt-branch.ll (+20-20)
- (modified) llvm/test/CodeGen/RISCV/compress-opt-select.ll (+20-20)
- (modified) llvm/test/CodeGen/RISCV/compress.ll (+24-24)
- (modified) llvm/test/CodeGen/RISCV/option-nopic.ll (+3-3)
- (modified) llvm/test/CodeGen/RISCV/option-pic.ll (+2-2)
- (modified) llvm/test/CodeGen/RISCV/option-rvc.ll (+1-1)
- (modified) llvm/test/MC/RISCV/XTHeadBa-valid.s (+2-2)
- (modified) llvm/test/MC/RISCV/attribute-with-insts.s (+2-2)
- (modified) llvm/test/MC/RISCV/compress-rv32d.s (+8-8)
- (modified) llvm/test/MC/RISCV/compress-rv32f.s (+4-4)
- (modified) llvm/test/MC/RISCV/compress-rv32i.s (+4-4)
- (modified) llvm/test/MC/RISCV/compress-rv64i.s (+2-2)
- (modified) llvm/test/MC/RISCV/corev/XCValu-valid.s (+1-1)
- (modified) llvm/test/MC/RISCV/corev/XCVbi.s (+6-6)
- (modified) llvm/test/MC/RISCV/corev/XCVbitmanip.s (+1-1)
- (modified) llvm/test/MC/RISCV/corev/XCVelw-valid.s (+1-1)
- (modified) llvm/test/MC/RISCV/corev/XCVmac-valid.s (+1-1)
- (modified) llvm/test/MC/RISCV/corev/XCVmem-valid.s (+1-1)
- (modified) llvm/test/MC/RISCV/corev/XCVsimd.s (+1-1)
- (modified) llvm/test/MC/RISCV/csr-aliases.s (+16-16)
- (modified) llvm/test/MC/RISCV/fixups.s (+1-1)
- (modified) llvm/test/MC/RISCV/hilo-constaddr.s (+2-2)
- (modified) llvm/test/MC/RISCV/insn.s (+12-12)
- (modified) llvm/test/MC/RISCV/insn_c.s (+7-7)
- (modified) llvm/test/MC/RISCV/nop-slide.s (+5-5)
- (modified) llvm/test/MC/RISCV/numeric-reg-names.s (+1-1)
- (modified) llvm/test/MC/RISCV/option-arch.s (+11-11)
- (modified) llvm/test/MC/RISCV/option-mix.s (+20-20)
- (modified) llvm/test/MC/RISCV/option-pushpop.s (+2-2)
- (modified) llvm/test/MC/RISCV/option-rvc.s (+4-4)
- (modified) llvm/test/MC/RISCV/pcrel-fixups.s (+4-4)
- (removed) llvm/test/MC/RISCV/print-imm-hex.s (-42)
- (modified) llvm/test/MC/RISCV/rv32c-aliases-valid.s (+2-2)
- (modified) llvm/test/MC/RISCV/rv32c-only-valid.s (+1-1)
- (modified) llvm/test/MC/RISCV/rv32c-valid.s (+4-4)
- (modified) llvm/test/MC/RISCV/rv32d-valid.s (+2-2)
- (modified) llvm/test/MC/RISCV/rv32dc-valid.s (+2-2)
- (modified) llvm/test/MC/RISCV/rv32e-valid.s (+2-2)
- (modified) llvm/test/MC/RISCV/rv32f-valid.s (+2-2)
- (modified) llvm/test/MC/RISCV/rv32fc-aliases-valid.s (+1-1)
- (modified) llvm/test/MC/RISCV/rv32fc-valid.s (+2-2)
- (modified) llvm/test/MC/RISCV/rv32i-aliases-valid.s (+2-2)
- (modified) llvm/test/MC/RISCV/rv32i-only-valid.s (+1-1)
- (modified) llvm/test/MC/RISCV/rv32i-valid.s (+2-2)
- (modified) llvm/test/MC/RISCV/rv32xtheadbs-valid.s (+2-2)
- (modified) llvm/test/MC/RISCV/rv32xtheadfmemidx-valid.s (+1-1)
- (modified) llvm/test/MC/RISCV/rv32zbb-aliases-valid.s (+2-2)
- (modified) llvm/test/MC/RISCV/rv32zbb-only-valid.s (+1-1)
- (modified) llvm/test/MC/RISCV/rv32zbkb-valid.s (+2-2)
- (modified) llvm/test/MC/RISCV/rv32zbs-aliases-valid.s (+2-2)
- (modified) llvm/test/MC/RISCV/rv32zbs-valid.s (+2-2)
- (modified) llvm/test/MC/RISCV/rv32zcb-valid.s (+2-2)
- (modified) llvm/test/MC/RISCV/rv32zcmt-valid.s (+2-2)
- (modified) llvm/test/MC/RISCV/rv32zfbfmin-valid.s (+2-2)
- (modified) llvm/test/MC/RISCV/rv32zfh-valid.s (+2-2)
- (modified) llvm/test/MC/RISCV/rv32zfhmin-valid.s (+2-2)
- (modified) llvm/test/MC/RISCV/rv32zicbop-valid.s (+2-2)
- (modified) llvm/test/MC/RISCV/rv32zknd-only-valid.s (+1-1)
- (modified) llvm/test/MC/RISCV/rv32zkne-only-valid.s (+1-1)
- (modified) llvm/test/MC/RISCV/rv32zksed-valid.s (+2-2)
- (modified) llvm/test/MC/RISCV/rv64-machine-csr-names.s (+1-1)
- (modified) llvm/test/MC/RISCV/rv64-user-csr-names.s (+32-32)
- (modified) llvm/test/MC/RISCV/rv64c-aliases-valid.s (+2-2)
- (modified) llvm/test/MC/RISCV/rv64c-hints-valid.s (+2-2)
- (modified) llvm/test/MC/RISCV/rv64c-valid.s (+2-2)
- (modified) llvm/test/MC/RISCV/rv64dc-valid.s (+2-2)
- (modified) llvm/test/MC/RISCV/rv64e-valid.s (+1-1)
- (modified) llvm/test/MC/RISCV/rv64i-aliases-valid.s (+2-2)
- (modified) llvm/test/MC/RISCV/rv64i-valid.s (+1-1)
- (modified) llvm/test/MC/RISCV/rv64xtheadfmemidx-valid.s (+1-1)
- (modified) llvm/test/MC/RISCV/rv64zba-aliases-valid.s (+2-2)
- (modified) llvm/test/MC/RISCV/rv64zbb-aliases-valid.s (+2-2)
- (modified) llvm/test/MC/RISCV/rv64zbb-valid.s (+1-1)
- (modified) llvm/test/MC/RISCV/rv64zbkb-valid.s (+1-1)
- (modified) llvm/test/MC/RISCV/rv64zbs-aliases-valid.s (+2-2)
- (modified) llvm/test/MC/RISCV/rv64zknd-only-valid.s (+1-1)
- (modified) llvm/test/MC/RISCV/rv64zkne-only-valid.s (+1-1)
- (modified) llvm/test/MC/RISCV/rvc-aliases-valid.s (+2-2)
- (modified) llvm/test/MC/RISCV/rvc-hints-valid.s (+3-3)
- (modified) llvm/test/MC/RISCV/rvd-aliases-valid.s (+4-4)
- (modified) llvm/test/MC/RISCV/rvdc-aliases-valid.s (+2-2)
- (modified) llvm/test/MC/RISCV/rvf-aliases-valid.s (+4-4)
- (modified) llvm/test/MC/RISCV/rvi-aliases-valid.s (+4-4)
- (modified) llvm/test/MC/RISCV/rvi-alternate-abi-names.s (+2-2)
- (modified) llvm/test/MC/RISCV/rvv/add.s (+1-1)
- (modified) llvm/test/MC/RISCV/rvv/and.s (+1-1)
- (modified) llvm/test/MC/RISCV/rvv/clip.s (+1-1)
- (modified) llvm/test/MC/RISCV/rvv/compare.s (+20-20)
- (modified) llvm/test/MC/RISCV/rvv/mv.s (+1-1)
- (modified) llvm/test/MC/RISCV/rvv/or.s (+2-2)
- (modified) llvm/test/MC/RISCV/rvv/others.s (+1-1)
- (modified) llvm/test/MC/RISCV/rvv/rv32-immediate.s (+1-1)
- (modified) llvm/test/MC/RISCV/rvv/shift.s (+1-1)
- (modified) llvm/test/MC/RISCV/rvv/snippet.s (+3-3)
- (modified) llvm/test/MC/RISCV/rvv/sub.s (+1-1)
- (modified) llvm/test/MC/RISCV/rvv/vsetvl-invalid.s (+10-10)
- (modified) llvm/test/MC/RISCV/rvv/vsetvl.s (+1-1)
- (modified) llvm/test/MC/RISCV/rvv/xor.s (+1-1)
- (modified) llvm/test/MC/RISCV/rvv/xsfvcp.s (+2-2)
- (modified) llvm/test/MC/RISCV/rvv/zvbb.s (+1-1)
- (modified) llvm/test/MC/RISCV/rvv/zvfbfwma.s (+2-2)
- (modified) llvm/test/MC/RISCV/rvv/zvkb.s (+1-1)
- (modified) llvm/test/MC/RISCV/rvv/zvkned.s (+1-1)
- (modified) llvm/test/MC/RISCV/rvv/zvksed.s (+1-1)
- (modified) llvm/test/MC/RISCV/rvv/zvksh.s (+1-1)
- (modified) llvm/test/MC/RISCV/rvzfh-aliases-valid.s (+4-4)
- (modified) llvm/test/MC/RISCV/zicfilp-valid.s (+2-2)
- (modified) llvm/test/tools/llvm-objdump/ELF/RISCV/branches.s (+4-4)
- (modified) llvm/test/tools/llvm-objdump/ELF/RISCV/multi-instr-target.s (+1-1)
- (modified) llvm/test/tools/llvm-objdump/ELF/RISCV/tag-riscv-arch.s (+1-1)
``````````diff
diff --git a/bolt/test/RISCV/call-annotations.s b/bolt/test/RISCV/call-annotations.s
index ff99e0f1dfd848..1a8ac1571f0be2 100644
--- a/bolt/test/RISCV/call-annotations.s
+++ b/bolt/test/RISCV/call-annotations.s
@@ -16,13 +16,13 @@ f:
// CHECK-LABEL: Binary Function "_start" after building cfg {
// CHECK: auipc ra, f
-// CHECK-NEXT: jalr ra, -0x4(ra) # Offset: 4
+// CHECK-NEXT: jalr ra, -4(ra) # Offset: 4
// CHECK-NEXT: jal ra, f # Offset: 8
// CHECK-NEXT: jal zero, f # TAILCALL # Offset: 12
// CHECK-LABEL: Binary Function "long_tail" after building cfg {
// CHECK: auipc t1, f
-// CHECK-NEXT: jalr zero, -0x18(t1) # TAILCALL # Offset: 8
+// CHECK-NEXT: jalr zero, -24(t1) # TAILCALL # Offset: 8
// CHECK-LABEL: Binary Function "compressed_tail" after building cfg {
// CHECK: jr a0 # TAILCALL # Offset: 0
diff --git a/bolt/test/RISCV/relax.s b/bolt/test/RISCV/relax.s
index bf9287e1d0d85a..01682e4405b715 100644
--- a/bolt/test/RISCV/relax.s
+++ b/bolt/test/RISCV/relax.s
@@ -7,7 +7,7 @@
// CHECK: Binary Function "_start" after building cfg {
// CHECK: jal ra, near_f
// CHECK-NEXT: auipc ra, far_f at plt
-// CHECK-NEXT: jalr ra, 0xc(ra)
+// CHECK-NEXT: jalr ra, 12(ra)
// CHECK-NEXT: j near_f
// CHECK: Binary Function "_start" after fix-riscv-calls {
@@ -17,8 +17,8 @@
// OBJDUMP: 0000000000600000 <_start>:
// OBJDUMP-NEXT: jal 0x600040 <near_f>
-// OBJDUMP-NEXT: auipc ra, 0x200
-// OBJDUMP-NEXT: jalr 0x7c(ra)
+// OBJDUMP-NEXT: auipc ra, 512
+// OBJDUMP-NEXT: jalr 124(ra)
// OBJDUMP-NEXT: j 0x600040 <near_f>
// OBJDUMP: 0000000000600040 <near_f>:
// OBJDUMP: 0000000000800080 <far_f>:
diff --git a/bolt/test/RISCV/reloc-tls.s b/bolt/test/RISCV/reloc-tls.s
index d6c8e492cab5d9..a4c7bd06de907c 100644
--- a/bolt/test/RISCV/reloc-tls.s
+++ b/bolt/test/RISCV/reloc-tls.s
@@ -4,10 +4,10 @@
// RUN: | FileCheck %s
// CHECK-LABEL: Binary Function "tls_le{{.*}}" after building cfg {
-// CHECK: lui a5, 0x0
+// CHECK: lui a5, 0
// CHECK-NEXT: add a5, a5, tp
-// CHECK-NEXT: lw t0, 0x0(a5)
-// CHECK-NEXT: sw t0, 0x0(a5)
+// CHECK-NEXT: lw t0, 0(a5)
+// CHECK-NEXT: sw t0, 0(a5)
// CHECK-LABEL: Binary Function "tls_ie" after building cfg {
// CHECK-LABEL: .LBB01
diff --git a/bolt/test/RISCV/reorder-blocks-reverse.s b/bolt/test/RISCV/reorder-blocks-reverse.s
index 6909fde59a4801..2da34844a5a841 100644
--- a/bolt/test/RISCV/reorder-blocks-reverse.s
+++ b/bolt/test/RISCV/reorder-blocks-reverse.s
@@ -23,9 +23,9 @@ _start:
// CHECK-NEXT: {{.*}}00: beq t0, t1, {{.*}} <_start+0x10>
// CHECK-NEXT: {{.*}}04: j {{.*}} <_start+0x16>
// CHECK-NEXT: {{.*}}08: ret
-// CHECK-NEXT: {{.*}}0a: li a0, 0x6
+// CHECK-NEXT: {{.*}}0a: li a0, 6
// CHECK-NEXT: {{.*}}0c: j {{.*}} <_start+0x8>
-// CHECK-NEXT: {{.*}}10: li a0, 0x5
+// CHECK-NEXT: {{.*}}10: li a0, 5
// CHECK-NEXT: {{.*}}12: j {{.*}} <_start+0x8>
// CHECK-NEXT: {{.*}}16: beq t0, t2, {{.*}} <_start+0xa>
// CHECK-NEXT: {{.*}}1a: j {{.*}} <_start+0x10>
diff --git a/bolt/test/RISCV/tls-le-gnu-ld.test b/bolt/test/RISCV/tls-le-gnu-ld.test
index 06e5bc0b5c82a0..c3ff08b30ee60d 100644
--- a/bolt/test/RISCV/tls-le-gnu-ld.test
+++ b/bolt/test/RISCV/tls-le-gnu-ld.test
@@ -7,5 +7,5 @@
// RUN: | FileCheck %s
// CHECK: Binary Function "_start" after building cfg {
-// CHECK: lw t0, 0x0(tp)
-// CHECK-NEXT: sw t0, 0x0(tp)
+// CHECK: lw t0, 0(tp)
+// CHECK-NEXT: sw t0, 0(tp)
diff --git a/lld/test/ELF/riscv-call.s b/lld/test/ELF/riscv-call.s
index 5fef156df0bb77..c4c89c35b7fed1 100644
--- a/lld/test/ELF/riscv-call.s
+++ b/lld/test/ELF/riscv-call.s
@@ -7,19 +7,19 @@
# RUN: ld.lld %t.rv64.o --defsym foo=_start+8 --defsym bar=_start -o %t.rv64
# RUN: llvm-objdump -d %t.rv32 | FileCheck %s
# RUN: llvm-objdump -d %t.rv64 | FileCheck %s
-# CHECK: 97 00 00 00 auipc ra, 0x0
-# CHECK-NEXT: e7 80 80 00 jalr 0x8(ra)
-# CHECK: 97 00 00 00 auipc ra, 0x0
-# CHECK-NEXT: e7 80 80 ff jalr -0x8(ra)
+# CHECK: 97 00 00 00 auipc ra, 0
+# CHECK-NEXT: e7 80 80 00 jalr 8(ra)
+# CHECK: 97 00 00 00 auipc ra, 0
+# CHECK-NEXT: e7 80 80 ff jalr -8(ra)
# RUN: ld.lld %t.rv32.o --defsym foo=_start+0x7ffff7ff --defsym bar=_start+8-0x80000800 -o %t.rv32.limits
# RUN: ld.lld %t.rv64.o --defsym foo=_start+0x7ffff7ff --defsym bar=_start+8-0x80000800 -o %t.rv64.limits
# RUN: llvm-objdump -d %t.rv32.limits | FileCheck --check-prefix=LIMITS %s
# RUN: llvm-objdump -d %t.rv64.limits | FileCheck --check-prefix=LIMITS %s
-# LIMITS: 97 f0 ff 7f auipc ra, 0x7ffff
-# LIMITS-NEXT: e7 80 f0 7f jalr 0x7ff(ra)
-# LIMITS-NEXT: 97 00 00 80 auipc ra, 0x80000
-# LIMITS-NEXT: e7 80 00 80 jalr -0x800(ra)
+# LIMITS: 97 f0 ff 7f auipc ra, 524287
+# LIMITS-NEXT: e7 80 f0 7f jalr 2047(ra)
+# LIMITS-NEXT: 97 00 00 80 auipc ra, 524288
+# LIMITS-NEXT: e7 80 00 80 jalr -2048(ra)
# RUN: ld.lld %t.rv32.o --defsym foo=_start+0x7ffff800 --defsym bar=_start+8-0x80000801 -o %t
# RUN: not ld.lld %t.rv64.o --defsym foo=_start+0x7ffff800 --defsym bar=_start+8-0x80000801 -o /dev/null 2>&1 | \
diff --git a/lld/test/ELF/riscv-hi20-lo12.s b/lld/test/ELF/riscv-hi20-lo12.s
index 85861432db0bdf..4a0c619ae0d2fa 100644
--- a/lld/test/ELF/riscv-hi20-lo12.s
+++ b/lld/test/ELF/riscv-hi20-lo12.s
@@ -7,23 +7,23 @@
# RUN: ld.lld %t.rv64.o --defsym foo=0 --defsym bar=42 -o %t.rv64
# RUN: llvm-objdump -d %t.rv32 | FileCheck %s
# RUN: llvm-objdump -d %t.rv64 | FileCheck %s
-# CHECK: 37 05 00 00 lui a0, 0x0
+# CHECK: 37 05 00 00 lui a0, 0
# CHECK-NEXT: 13 05 05 00 mv a0, a0
-# CHECK-NEXT: 23 20 a5 00 sw a0, 0x0(a0)
-# CHECK-NEXT: b7 05 00 00 lui a1, 0x0
-# CHECK-NEXT: 93 85 a5 02 addi a1, a1, 0x2a
-# CHECK-NEXT: 23 a5 b5 02 sw a1, 0x2a(a1)
+# CHECK-NEXT: 23 20 a5 00 sw a0, 0(a0)
+# CHECK-NEXT: b7 05 00 00 lui a1, 0
+# CHECK-NEXT: 93 85 a5 02 addi a1, a1, 42
+# CHECK-NEXT: 23 a5 b5 02 sw a1, 42(a1)
# RUN: ld.lld %t.rv32.o --defsym foo=0x7ffff7ff --defsym bar=0x7ffff800 -o %t.rv32.limits
# RUN: ld.lld %t.rv64.o --defsym foo=0x7ffff7ff --defsym bar=0xffffffff7ffff800 -o %t.rv64.limits
# RUN: llvm-objdump -d %t.rv32.limits | FileCheck --check-prefix=LIMITS %s
# RUN: llvm-objdump -d %t.rv64.limits | FileCheck --check-prefix=LIMITS %s
-# LIMITS: 37 f5 ff 7f lui a0, 0x7ffff
-# LIMITS-NEXT: 13 05 f5 7f addi a0, a0, 0x7ff
-# LIMITS-NEXT: a3 2f a5 7e sw a0, 0x7ff(a0)
-# LIMITS-NEXT: b7 05 00 80 lui a1, 0x80000
-# LIMITS-NEXT: 93 85 05 80 addi a1, a1, -0x800
-# LIMITS-NEXT: 23 a0 b5 80 sw a1, -0x800(a1)
+# LIMITS: 37 f5 ff 7f lui a0, 524287
+# LIMITS-NEXT: 13 05 f5 7f addi a0, a0, 2047
+# LIMITS-NEXT: a3 2f a5 7e sw a0, 2047(a0)
+# LIMITS-NEXT: b7 05 00 80 lui a1, 524288
+# LIMITS-NEXT: 93 85 05 80 addi a1, a1, -2048
+# LIMITS-NEXT: 23 a0 b5 80 sw a1, -2048(a1)
# RUN: not ld.lld %t.rv64.o --defsym foo=0x7ffff800 --defsym bar=0xffffffff7ffff7ff -o /dev/null 2>&1 | FileCheck --check-prefix ERROR %s
# ERROR: relocation R_RISCV_HI20 out of range: 524288 is not in [-524288, 524287]; references 'foo'
diff --git a/lld/test/ELF/riscv-ifunc-nonpreemptible.s b/lld/test/ELF/riscv-ifunc-nonpreemptible.s
index 21c6075451104b..0ab322961898b0 100644
--- a/lld/test/ELF/riscv-ifunc-nonpreemptible.s
+++ b/lld/test/ELF/riscv-ifunc-nonpreemptible.s
@@ -26,13 +26,13 @@
# SYM32: 0001190 0 FUNC GLOBAL DEFAULT {{.*}} func
# DIS32: <_start>:
-# DIS32-NEXT: 1180: auipc a0, 0x0
-# DIS32-NEXT: addi a0, a0, 0x10
+# DIS32-NEXT: 1180: auipc a0, 0
+# DIS32-NEXT: addi a0, a0, 16
# DIS32: Disassembly of section .iplt:
# DIS32: <func>:
## 32-bit: &.got.plt[func]-. = 0x3220-0x1190 = 4096*2+144
-# DIS32-NEXT: 1190: auipc t3, 0x2
-# DIS32-NEXT: lw t3, 0x90(t3)
+# DIS32-NEXT: 1190: auipc t3, 2
+# DIS32-NEXT: lw t3, 144(t3)
# DIS32-NEXT: jalr t1, t3
# DIS32-NEXT: nop
@@ -47,13 +47,13 @@
# SYM64: 000000000001270 0 FUNC GLOBAL DEFAULT {{.*}} func
# DIS64: <_start>:
-# DIS64-NEXT: 1264: auipc a0, 0x0
-# DIS64-NEXT: addi a0, a0, 0xc
+# DIS64-NEXT: 1264: auipc a0, 0
+# DIS64-NEXT: addi a0, a0, 12
# DIS64: Disassembly of section .iplt:
# DIS64: <func>:
## 64-bit: &.got.plt[func]-. = 0x3380-0x1270 = 4096*2+272
-# DIS64-NEXT: 1270: auipc t3, 0x2
-# DIS64-NEXT: ld t3, 0x110(t3)
+# DIS64-NEXT: 1270: auipc t3, 2
+# DIS64-NEXT: ld t3, 272(t3)
# DIS64-NEXT: jalr t1, t3
# DIS64-NEXT: nop
diff --git a/lld/test/ELF/riscv-pcrel-hilo.s b/lld/test/ELF/riscv-pcrel-hilo.s
index 9f9e7634e2d901..a553e29d048573 100644
--- a/lld/test/ELF/riscv-pcrel-hilo.s
+++ b/lld/test/ELF/riscv-pcrel-hilo.s
@@ -11,23 +11,23 @@
# RUN: ld.lld -pie %t.rv64.o --defsym foo=_start+12 --defsym bar=_start -o %t.rv64
# RUN: llvm-objdump -d --no-show-raw-insn %t.rv32 | FileCheck %s
# RUN: llvm-objdump -d --no-show-raw-insn %t.rv64 | FileCheck %s
-# CHECK: auipc a0, 0x0
-# CHECK-NEXT: addi a0, a0, 0xc
-# CHECK-NEXT: sw zero, 0xc(a0)
-# CHECK: auipc a0, 0x0
-# CHECK-NEXT: addi a0, a0, -0xc
-# CHECK-NEXT: sw zero, -0xc(a0)
+# CHECK: auipc a0, 0
+# CHECK-NEXT: addi a0, a0, 12
+# CHECK-NEXT: sw zero, 12(a0)
+# CHECK: auipc a0, 0
+# CHECK-NEXT: addi a0, a0, -12
+# CHECK-NEXT: sw zero, -12(a0)
# RUN: ld.lld %t.rv32.o --defsym foo=_start+0x7ffff7ff --defsym bar=_start+12-0x80000800 -o %t.rv32.limits
# RUN: ld.lld %t.rv64.o --defsym foo=_start+0x7ffff7ff --defsym bar=_start+12-0x80000800 -o %t.rv64.limits
# RUN: llvm-objdump -d --no-show-raw-insn %t.rv32.limits | FileCheck --check-prefix=LIMITS %s
# RUN: llvm-objdump -d --no-show-raw-insn %t.rv64.limits | FileCheck --check-prefix=LIMITS %s
-# LIMITS: auipc a0, 0x7ffff
-# LIMITS-NEXT: addi a0, a0, 0x7ff
-# LIMITS-NEXT: sw zero, 0x7ff(a0)
-# LIMITS: auipc a0, 0x80000
-# LIMITS-NEXT: addi a0, a0, -0x800
-# LIMITS-NEXT: sw zero, -0x800(a0)
+# LIMITS: auipc a0, 524287
+# LIMITS-NEXT: addi a0, a0, 2047
+# LIMITS-NEXT: sw zero, 2047(a0)
+# LIMITS: auipc a0, 524288
+# LIMITS-NEXT: addi a0, a0, -2048
+# LIMITS-NEXT: sw zero, -2048(a0)
# RUN: ld.lld %t.rv32.o --defsym foo=_start+0x7ffff800 --defsym bar=_start+12-0x80000801 -o %t
# RUN: not ld.lld %t.rv64.o --defsym foo=_start+0x7ffff800 --defsym bar=_start+12-0x80000801 -o /dev/null 2>&1 | FileCheck --check-prefix=ERROR %s
diff --git a/lld/test/ELF/riscv-plt.s b/lld/test/ELF/riscv-plt.s
index 4b3649e3ba8df9..489eadd68b0e2f 100644
--- a/lld/test/ELF/riscv-plt.s
+++ b/lld/test/ELF/riscv-plt.s
@@ -46,47 +46,47 @@
# DIS: <_start>:
## Direct call
## foo - . = 0x11020-0x11000 = 32
-# DIS-NEXT: 11000: auipc ra, 0x0
-# DIS-NEXT: jalr 0x20(ra)
+# DIS-NEXT: 11000: auipc ra, 0
+# DIS-NEXT: jalr 32(ra)
## bar at plt - . = 0x11050-0x11008 = 72
-# DIS-NEXT: 11008: auipc ra, 0x0
-# DIS-NEXT: jalr 0x48(ra)
+# DIS-NEXT: 11008: auipc ra, 0
+# DIS-NEXT: jalr 72(ra)
## bar at plt - . = 0x11050-0x11010 = 64
-# DIS-NEXT: 11010: auipc ra, 0x0
-# DIS-NEXT: jalr 0x40(ra)
+# DIS-NEXT: 11010: auipc ra, 0
+# DIS-NEXT: jalr 64(ra)
## weak at plt - . = 0x11060-0x11018 = 72
-# DIS-NEXT: 11018: auipc ra, 0x0
-# DIS-NEXT: jalr 0x48(ra)
+# DIS-NEXT: 11018: auipc ra, 0
+# DIS-NEXT: jalr 72(ra)
# DIS: <foo>:
# DIS-NEXT: 11020:
# DIS: Disassembly of section .plt:
# DIS: <.plt>:
-# DIS-NEXT: auipc t2, 0x2
+# DIS-NEXT: auipc t2, 2
# DIS-NEXT: sub t1, t1, t3
## .got.plt - .plt = 0x13068 - 0x11030 = 4096*2+56
-# DIS32-NEXT: lw t3, 0x38(t2)
-# DIS64-NEXT: ld t3, 0xa0(t2)
-# DIS-NEXT: addi t1, t1, -0x2c
-# DIS32-NEXT: addi t0, t2, 0x38
-# DIS64-NEXT: addi t0, t2, 0xa0
-# DIS32-NEXT: srli t1, t1, 0x2
-# DIS64-NEXT: srli t1, t1, 0x1
-# DIS32-NEXT: lw t0, 0x4(t0)
-# DIS64-NEXT: ld t0, 0x8(t0)
+# DIS32-NEXT: lw t3, 56(t2)
+# DIS64-NEXT: ld t3, 160(t2)
+# DIS-NEXT: addi t1, t1, -44
+# DIS32-NEXT: addi t0, t2, 56
+# DIS64-NEXT: addi t0, t2, 160
+# DIS32-NEXT: srli t1, t1, 2
+# DIS64-NEXT: srli t1, t1, 1
+# DIS32-NEXT: lw t0, 4(t0)
+# DIS64-NEXT: ld t0, 8(t0)
# DIS-NEXT: jr t3
## 32-bit: &.got.plt[bar]-. = 0x13070-0x11050 = 4096*2+32
-# DIS: 11050: auipc t3, 0x2
-# DIS32-NEXT: lw t3, 0x20(t3)
-# DIS64-NEXT: ld t3, 0x90(t3)
+# DIS: 11050: auipc t3, 2
+# DIS32-NEXT: lw t3, 32(t3)
+# DIS64-NEXT: ld t3, 144(t3)
# DIS-NEXT: jalr t1, t3
# DIS-NEXT: nop
## 32-bit: &.got.plt[weak]-. = 0x13074-0x11060 = 4096*2+20
-# DIS: 11060: auipc t3, 0x2
-# DIS32-NEXT: lw t3, 0x14(t3)
-# DIS64-NEXT: ld t3, 0x88(t3)
+# DIS: 11060: auipc t3, 2
+# DIS32-NEXT: lw t3, 20(t3)
+# DIS64-NEXT: ld t3, 136(t3)
# DIS-NEXT: jalr t1, t3
# DIS-NEXT: nop
diff --git a/lld/test/ELF/riscv-relax-align-rvc.s b/lld/test/ELF/riscv-relax-align-rvc.s
index 8980e18ea876b6..4efce68e85d5b2 100644
--- a/lld/test/ELF/riscv-relax-align-rvc.s
+++ b/lld/test/ELF/riscv-relax-align-rvc.s
@@ -22,67 +22,67 @@
# CHECK-DAG: 00010000 g .text {{0*}}36 _start
# CHECK: <_start>:
-# CHECK-NEXT: c.addi a0, 0x1
+# CHECK-NEXT: c.addi a0, 1
# CHECK-EMPTY:
# CHECK-NEXT: <a>:
# CHECK-NEXT: c.nop
-# CHECK-NEXT: addi zero, zero, 0x0
-# CHECK-NEXT: addi zero, zero, 0x0
-# CHECK-NEXT: addi zero, zero, 0x0
+# CHECK-NEXT: addi zero, zero, 0
+# CHECK-NEXT: addi zero, zero, 0
+# CHECK-NEXT: addi zero, zero, 0
# CHECK-EMPTY:
# CHECK-NEXT: <b>:
-# CHECK-NEXT: 10010: c.addi a0, 0x2
+# CHECK-NEXT: 10010: c.addi a0, 2
# CHECK-EMPTY:
# CHECK-NEXT: <c>:
-# CHECK-NEXT: c.addi a0, 0x3
-# CHECK-NEXT: addi zero, zero, 0x0
-# CHECK-NEXT: addi zero, zero, 0x0
-# CHECK-NEXT: addi zero, zero, 0x0
+# CHECK-NEXT: c.addi a0, 3
+# CHECK-NEXT: addi zero, zero, 0
+# CHECK-NEXT: addi zero, zero, 0
+# CHECK-NEXT: addi zero, zero, 0
# CHECK-EMPTY:
# CHECK-NEXT: <d>:
-# CHECK-NEXT: 10020: c.addi a0, 0x4
-# CHECK-NEXT: c.addi a0, 0x5
-# CHECK-NEXT: addi zero, zero, 0x0
-# CHECK-NEXT: addi zero, zero, 0x0
-# CHECK-NEXT: addi zero, zero, 0x0
-# CHECK-NEXT: 10030: c.addi a0, 0x6
-# CHECK-NEXT: c.addi a0, 0x7
-# CHECK-NEXT: c.addi a0, 0x8
+# CHECK-NEXT: 10020: c.addi a0, 4
+# CHECK-NEXT: c.addi a0, 5
+# CHECK-NEXT: addi zero, zero, 0
+# CHECK-NEXT: addi zero, zero, 0
+# CHECK-NEXT: addi zero, zero, 0
+# CHECK-NEXT: 10030: c.addi a0, 6
+# CHECK-NEXT: c.addi a0, 7
+# CHECK-NEXT: c.addi a0, 8
# CHECK-EMPTY:
# CHECK: <.text2>:
-# CHECK-NEXT: addi a0, a1, 0x1
-# CHECK-NEXT: c.addi a0, 0x1
+# CHECK-NEXT: addi a0, a1, 1
+# CHECK-NEXT: c.addi a0, 1
# CHECK-NEXT: c.nop
-# CHECK-NEXT: c.addi a0, 0x2
+# CHECK-NEXT: c.addi a0, 2
.global _start
_start:
- c.addi a0, 0x1
+ c.addi a0, 1
a:
.balign 16
b:
- c.addi a0, 0x2
+ c.addi a0, 2
c:
- c.addi a0, 0x3
+ c.addi a0, 3
.balign 32
.size a, . - a
d:
- c.addi a0, 0x4
- c.addi a0, 0x5
+ c.addi a0, 4
+ c.addi a0, 5
.balign 16
.size c, . - c
- c.addi a0, 0x6
+ c.addi a0, 6
.size b, . - b
- c.addi a0, 0x7
+ c.addi a0, 7
.balign 4
- c.addi a0, 0x8
+ c.addi a0, 8
.size d, . - d
.size _start, . - _start
.section .text2,"ax"
.balign 16
- addi a0, a1, 0x1
- c.addi a0, 0x1
+ addi a0, a1, 1
+ c.addi a0, 1
.balign 8
- c.addi a0, 0x2
+ c.addi a0, 2
diff --git a/lld/test/ELF/riscv-relax-align.s b/lld/test/ELF/riscv-relax-align.s
index 3efc774f76dd4e..8a46d601d4ef03 100644
--- a/lld/test/ELF/riscv-relax-align.s
+++ b/lld/test/ELF/riscv-relax-align.s
@@ -29,49 +29,49 @@
# CHECK-DAG: 00010000 g .text {{0*}}38 _start
# CHECK: <_start>:
-# CHECK-NEXT: addi a0, a0, 0x1
+# CHECK-NEXT: addi a0, a0, 1
# CHECK-EMPTY:
# CHECK-NEXT: <a>:
-# CHECK-NEXT: addi a0, a0, 0x2
+# CHECK-NEXT: addi a0, a0, 2
# CHECK-EMPTY:
# CHECK-NEXT: <b>:
-# CHECK-NEXT: addi zero, zero, 0x0
-# CHECK-NEXT: addi zero, zero, 0x0
-# CHECK-NEXT: 10010: addi a0, a0, 0x3
+# CHECK-NEXT: addi zero, zero, 0
+# CHECK-NEXT: addi zero, zero, 0
+# CHECK-NEXT: 10010: addi a0, a0, 3
# CHECK-EMPTY:
# CHECK-NEXT: <c>:
-# CHECK-NEXT: addi a0, a0, 0x4
-# CHECK-NEXT: addi a0, a0, 0x5
-# CHECK-NEXT: addi zero, zero, 0x0
-# CHECK-NEXT: 10020: addi a0, a0, 0x6
-# CHECK-NEXT: addi a0, a0, 0x7
-# CHECK-NEXT: addi zero, zero, 0x0
-# CHECK-NEXT: addi zero, zero, 0x0
-# CHECK-NEXT: 10030: addi a0, a0, 0x8
-# CHECK-NEXT: addi a0, a0, 0x9
+# CHECK-NEXT: addi a0, a0, 4
+# CHECK-NEXT: addi a0, a0, 5
+# CHECK-NEXT: addi zero, zero, 0
+# CHECK-NEXT: 10020: addi a0, a0, 6
+# CHECK-NEXT: addi a0, a0, 7
+# CHECK-NEXT: addi zero, zero, 0
+# CHECK-NEXT: addi zero, zero, 0
+# CHECK-NEXT: 10030: addi a0, a0, 8
+# CHECK-NEXT: addi a0, a0, 9
# CHECK-EMPTY:
# CHECK: <e>:
-# CHECK-NEXT: addi a0, a0, 0x1
+# CHECK-NEXT: addi a0, a0, 1
# CHECK-EMPTY:
# CHECK-NEXT: <f>:
-# CHECK-NEXT: 10044: addi a0, a0, 0x2
-# CHECK-NEXT: addi zero, zero, 0x0
-# CHECK-NEXT: addi zero, zero, 0x0
-# CHECK-NEXT: addi zero, zero, 0x0
-# CHECK-NEXT: addi zero, zero, 0x0
-# CHECK-NEXT: addi zero, zero, 0x0
-# CHECK-NEXT: addi zero, zero, 0x0
-# CHECK-NEXT: 10060: addi a0, a0, 0x3
+# CHECK-NEXT: 10044: addi a0, a0, 2
+# CHECK-NEXT: addi zero, zero, 0
+# CHECK-NEXT: addi zero, zero, 0
+# CHECK-NEXT: addi zero, zero, 0
+# CHECK-NEXT: addi zero, zero, 0
+# CHECK-NEXT: addi zero, zero, 0
+# CHECK-NEXT: addi zero, zero, 0
+# CHECK-NEXT: 10060: addi a0, a0, 3
# CHECK-EMPTY:
## _start-0x10070 = 0x10000-0x10070 = -112
# CHECK: <.L1>:
-# CHECK-NEXT: 10070: auipc a0, 0x0
-# CHECK-NEXT: addi a0, a0, -0x70
-# CHECK-NEXT: addi zero, zero, 0x0
-# CHECK-NEXT: addi zero, zero, 0x0
-# CHECK-NEXT: auipc a0, 0x0
-# CHECK-NEXT: addi a0, a0, -0x70
+# CHECK-NEXT: 10070: auipc a0, 0
+# CHECK-NEXT: addi a0, a0, -112
+# CHECK-NEXT: addi zero, zero, 0
+# CHECK-NEXT: addi zero, zero, 0
+# CHECK-NEXT: auipc a0, 0
+# CHECK-NEXT: addi a0, a0, -112
# CHECK-EMPTY:
# GC-DAG: 00010004 l .text {{0*}}1c a
@@ -82,58 +82,58 @@
# GC-NOT: <d>:
# CHECKR: <_start>:
-# CHECKR-NEXT: addi a0, a0, 0x1
+# CHECKR-NEXT: addi a0, a0, 1
# CHECKR-EMPTY:
# CHECKR-NEXT: <a>:
-# CHECKR-NEXT: addi a0, a0, 0x2
+# CHECKR-NEXT: addi a0, a0, 2
# CHECKR-EMPTY:
# CHECKR-NEXT: <b>:
-# CHECKR-NEXT: addi zero, zero, 0x0
+# CHECKR-NEXT: addi zero, zero, 0
# CHECKR-NEXT: 0000000000000008: R_RISCV_ALIGN *ABS*+0xc
-# CHECKR-NEXT: addi zero, zero, 0x0
-# CHECKR-NEXT: addi zero, zero, 0x0
-# CHECKR-NEXT: addi a0, a0, 0x3
+# CHECKR-NEXT: addi zero, zero, 0
+# CHECKR-NEXT: addi zero, zero, 0
+# CHECKR-NEXT: addi a0, a0, 3
# CHECKR-EMPTY:
# CHECKR-NEXT: <c>:
-# CHECKR-NEXT: addi a0, a0, 0x4
-# CHECKR-NEXT: addi a0, a0, 0x5
-# CHECKR-NEXT: addi zero, zero, 0x0
+# CHECKR-NEXT: addi a0, a0, 4
+# CHECKR-NEXT: addi ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/75561
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