[llvm] [RISCV] Support postRA vsetvl insertion pass (PR #70549)

[Piyou Chen via llvm-commits]

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@@ -100,6 +100,10 @@ static cl::opt<bool> EnableMISchedLoadClustering(
     cl::desc("Enable load clustering in the machine scheduler"),
     cl::init(false));
 
+static cl::opt<bool> EnableVSETVLIAfterRVVRegAlloc(
+    "riscv-vsetvli-after-rvv-regalloc", cl::Hidden,
+    cl::desc("vsetvl insertion after rvv regalloc"), cl::init(true));
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BeMg wrote:

I revert the testcase change and default disable `riscv-vsetvli-after-rvv-regalloc` in this patch. And add more testcase from  other lit that generate worse codegen into `splitRA-vsetvl.ll`.

https://github.com/llvm/llvm-project/pull/70549