[llvm] [RISCV] Prefer whole register loads and stores when VL=VLMAX (PR #75531)

[Craig Topper via llvm-commits]

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@@ -9838,6 +9838,20 @@ RISCVTargetLowering::lowerFixedLengthVectorLoadToRVV(SDValue Op,
   MVT XLenVT = Subtarget.getXLenVT();
   MVT ContainerVT = getContainerForFixedLengthVector(VT);
 
+  // If we know the exact VLEN and our fixed length vector completely fills
+  // the container, use a whole register load instead.
+  const auto [MinVLMAX, MaxVLMAX] =
+      RISCVTargetLowering::computeVLMAXBounds(ContainerVT, Subtarget);
+  if (MinVLMAX == MaxVLMAX && MinVLMAX == VT.getVectorNumElements() &&
+      getLMUL1VT(ContainerVT).bitsLE(ContainerVT)) {
+    SDValue NewLoad =
+      DAG.getLoad(ContainerVT, DL, Load->getChain(), Load->getBasePtr(),
+                  Load->getPointerInfo(), Load->getOriginalAlign(),
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topperc wrote:

Is there a getLoad signature that takes the MemOperand directly?

https://github.com/llvm/llvm-project/pull/75531