[clang] [llvm] [SystemZ] Support i128 as legal type in VRs (PR #74625)

[Ulrich Weigand via llvm-commits]

================
@@ -1466,7 +1509,15 @@ static SDValue convertValVTToLocVT(SelectionDAG &DAG, const SDLoc &DL,
 static SDValue lowerI128ToGR128(SelectionDAG &DAG, SDValue In) {
   SDLoc DL(In);
   SDValue Lo, Hi;
-  std::tie(Lo, Hi) = DAG.SplitScalar(In, DL, MVT::i64, MVT::i64);
+  if (DAG.getTargetLoweringInfo().isTypeLegal(MVT::i128)) {
+    Lo = DAG.getNode(ISD::TRUNCATE, DL, MVT::i64, In);
----------------
uweigand wrote:

Hmmm.  According to the specs, `EXTRACT_ELEMENT` (and therefore `SplitScalar`) is only supposed to be used on non-legal types, for values that will be broken up into multiple registers.   However, the actual implementation doesn't appear to verify this, and expands `EXTRACT_ELEMENT` even for a legal `i128`, to the same code ...

I would still prefer to not rely on that undocumented behavior, and use the explicit expansion.  Also, this keeps the implementation symmetrical to `lowerGR128ToI128`, and may be slightly more efficient as it omits generating and then immediately eliminating the `EXTRACT_ELEMENT` nodes.

https://github.com/llvm/llvm-project/pull/74625