[llvm] 7537c3c - [RISCV] Precommit test coverage for VLMAX encodable via vsetivli
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Thu Dec 14 09:43:30 PST 2023
Author: Philip Reames
Date: 2023-12-14T09:42:54-08:00
New Revision: 7537c3c452df36447719291bebc5589bdd5d1501
URL: https://github.com/llvm/llvm-project/commit/7537c3c452df36447719291bebc5589bdd5d1501
DIFF: https://github.com/llvm/llvm-project/commit/7537c3c452df36447719291bebc5589bdd5d1501.diff
LOG: [RISCV] Precommit test coverage for VLMAX encodable via vsetivli
Added:
Modified:
llvm/test/CodeGen/RISCV/rvv/load-add-store.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rvv/load-add-store.ll b/llvm/test/CodeGen/RISCV/rvv/load-add-store.ll
index bce5183f1a888f..3bb465ba998a23 100644
--- a/llvm/test/CodeGen/RISCV/rvv/load-add-store.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/load-add-store.ll
@@ -355,3 +355,148 @@ define void @vadd_vint64m8(ptr %pc, ptr %pa, ptr %pb) nounwind {
store <vscale x 8 x i64> %vc, ptr %pc
ret void
}
+
+
+define void @exact_vlen_vadd_vint8m1(ptr %pc, ptr %pa, ptr %pb) nounwind vscale_range(2,2) {
+; CHECK-LABEL: exact_vlen_vadd_vint8m1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vl1r.v v8, (a1)
+; CHECK-NEXT: vl1r.v v9, (a2)
+; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
+; CHECK-NEXT: vadd.vv v8, v8, v9
+; CHECK-NEXT: vs1r.v v8, (a0)
+; CHECK-NEXT: ret
+ %va = load <vscale x 8 x i8>, ptr %pa
+ %vb = load <vscale x 8 x i8>, ptr %pb
+ %vc = add <vscale x 8 x i8> %va, %vb
+ store <vscale x 8 x i8> %vc, ptr %pc
+ ret void
+}
+
+define void @exact_vlen_vadd_vint8m2(ptr %pc, ptr %pa, ptr %pb) nounwind vscale_range(2,2) {
+; CHECK-LABEL: exact_vlen_vadd_vint8m2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vl2r.v v8, (a1)
+; CHECK-NEXT: vl2r.v v10, (a2)
+; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
+; CHECK-NEXT: vadd.vv v8, v8, v10
+; CHECK-NEXT: vs2r.v v8, (a0)
+; CHECK-NEXT: ret
+ %va = load <vscale x 16 x i8>, ptr %pa
+ %vb = load <vscale x 16 x i8>, ptr %pb
+ %vc = add <vscale x 16 x i8> %va, %vb
+ store <vscale x 16 x i8> %vc, ptr %pc
+ ret void
+}
+
+define void @exact_vlen_vadd_vint8mf2(ptr %pc, ptr %pa, ptr %pb) nounwind vscale_range(2,2) {
+; CHECK-LABEL: exact_vlen_vadd_vint8mf2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vle8.v v8, (a1)
+; CHECK-NEXT: vle8.v v9, (a2)
+; CHECK-NEXT: vadd.vv v8, v8, v9
+; CHECK-NEXT: vse8.v v8, (a0)
+; CHECK-NEXT: ret
+ %va = load <vscale x 4 x i8>, ptr %pa
+ %vb = load <vscale x 4 x i8>, ptr %pb
+ %vc = add <vscale x 4 x i8> %va, %vb
+ store <vscale x 4 x i8> %vc, ptr %pc
+ ret void
+}
+
+define void @exact_vlen_vadd_vint8mf4(ptr %pc, ptr %pa, ptr %pb) nounwind vscale_range(2,2) {
+; CHECK-LABEL: exact_vlen_vadd_vint8mf4:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vle8.v v8, (a1)
+; CHECK-NEXT: vle8.v v9, (a2)
+; CHECK-NEXT: vadd.vv v8, v8, v9
+; CHECK-NEXT: vse8.v v8, (a0)
+; CHECK-NEXT: ret
+ %va = load <vscale x 2 x i8>, ptr %pa
+ %vb = load <vscale x 2 x i8>, ptr %pb
+ %vc = add <vscale x 2 x i8> %va, %vb
+ store <vscale x 2 x i8> %vc, ptr %pc
+ ret void
+}
+
+define void @exact_vlen_vadd_vint8mf8(ptr %pc, ptr %pa, ptr %pb) nounwind vscale_range(2,2) {
+; CHECK-LABEL: exact_vlen_vadd_vint8mf8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a3, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vle8.v v8, (a1)
+; CHECK-NEXT: vle8.v v9, (a2)
+; CHECK-NEXT: vadd.vv v8, v8, v9
+; CHECK-NEXT: vse8.v v8, (a0)
+; CHECK-NEXT: ret
+ %va = load <vscale x 1 x i8>, ptr %pa
+ %vb = load <vscale x 1 x i8>, ptr %pb
+ %vc = add <vscale x 1 x i8> %va, %vb
+ store <vscale x 1 x i8> %vc, ptr %pc
+ ret void
+}
+
+define void @exact_vlen_vadd_vint32m1(ptr %pc, ptr %pa, ptr %pb) nounwind vscale_range(2,2) {
+; CHECK-LABEL: exact_vlen_vadd_vint32m1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vl1re32.v v8, (a1)
+; CHECK-NEXT: vl1re32.v v9, (a2)
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; CHECK-NEXT: vadd.vv v8, v8, v9
+; CHECK-NEXT: vs1r.v v8, (a0)
+; CHECK-NEXT: ret
+ %va = load <vscale x 2 x i32>, ptr %pa
+ %vb = load <vscale x 2 x i32>, ptr %pb
+ %vc = add <vscale x 2 x i32> %va, %vb
+ store <vscale x 2 x i32> %vc, ptr %pc
+ ret void
+}
+
+define void @exact_vlen_vadd_vint32m2(ptr %pc, ptr %pa, ptr %pb) nounwind vscale_range(2,2) {
+; CHECK-LABEL: exact_vlen_vadd_vint32m2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vl2re32.v v8, (a1)
+; CHECK-NEXT: vl2re32.v v10, (a2)
+; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; CHECK-NEXT: vadd.vv v8, v8, v10
+; CHECK-NEXT: vs2r.v v8, (a0)
+; CHECK-NEXT: ret
+ %va = load <vscale x 4 x i32>, ptr %pa
+ %vb = load <vscale x 4 x i32>, ptr %pb
+ %vc = add <vscale x 4 x i32> %va, %vb
+ store <vscale x 4 x i32> %vc, ptr %pc
+ ret void
+}
+
+define void @exact_vlen_vadd_vint32m4(ptr %pc, ptr %pa, ptr %pb) nounwind vscale_range(2,2) {
+; CHECK-LABEL: exact_vlen_vadd_vint32m4:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vl4re32.v v8, (a1)
+; CHECK-NEXT: vl4re32.v v12, (a2)
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; CHECK-NEXT: vadd.vv v8, v8, v12
+; CHECK-NEXT: vs4r.v v8, (a0)
+; CHECK-NEXT: ret
+ %va = load <vscale x 8 x i32>, ptr %pa
+ %vb = load <vscale x 8 x i32>, ptr %pb
+ %vc = add <vscale x 8 x i32> %va, %vb
+ store <vscale x 8 x i32> %vc, ptr %pc
+ ret void
+}
+
+define void @exact_vlen_vadd_vint32m8(ptr %pc, ptr %pa, ptr %pb) nounwind vscale_range(2,2) {
+; CHECK-LABEL: exact_vlen_vadd_vint32m8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vl8re32.v v8, (a1)
+; CHECK-NEXT: vl8re32.v v16, (a2)
+; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma
+; CHECK-NEXT: vadd.vv v8, v8, v16
+; CHECK-NEXT: vs8r.v v8, (a0)
+; CHECK-NEXT: ret
+ %va = load <vscale x 16 x i32>, ptr %pa
+ %vb = load <vscale x 16 x i32>, ptr %pb
+ %vc = add <vscale x 16 x i32> %va, %vb
+ store <vscale x 16 x i32> %vc, ptr %pc
+ ret void
+}
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