[llvm] [RISCV] Improve llvm.reduce.fmaximum/minimum lowering (PR #75484)

[Craig Topper via llvm-commits]

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@@ -15650,6 +15651,22 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
 
     return SDValue();
   }
+  case ISD::VECREDUCE_FMAXIMUM:
+  case ISD::VECREDUCE_FMINIMUM: {
+    EVT RT = N->getValueType(0);
+    SDValue N0 = N->getOperand(0);
+
+    // Reduction fmax/fmin + separate reduction sum to propagate NaNs
+    unsigned ReducedMinMaxOpc = N->getOpcode() == ISD::VECREDUCE_FMAXIMUM
+                                    ? ISD::VECREDUCE_FMAX
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topperc wrote:

ISD::VECREDUCE_FMAX/FMIN aren't guaranteed to preserve the order of -0.0 and +0.0. If generic DAG combiner ends up seeing a constnat vector for some reason after this change, it might incorrectly fold it.

https://github.com/llvm/llvm-project/pull/75484