[llvm] 4888218 - [ARM] Do not emit unwind tables when saving LR around outlined call (#69611)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Dec 14 06:46:16 PST 2023
Author: ostannard
Date: 2023-12-14T14:46:13Z
New Revision: 4888218d0312f9126d8dd657d2ed568bf0572e9a
URL: https://github.com/llvm/llvm-project/commit/4888218d0312f9126d8dd657d2ed568bf0572e9a
DIFF: https://github.com/llvm/llvm-project/commit/4888218d0312f9126d8dd657d2ed568bf0572e9a.diff
LOG: [ARM] Do not emit unwind tables when saving LR around outlined call (#69611)
In some cases, the machine outliner needs to preserve LR across an
outlined call by pushing it onto the stack. Previously, this also
generated unwind table instructions, which is incorrect because EHABI
unwind tables cannot represent different stack frames a different points
in the function, so the extra unwind info applied to the entire
function.
The outliner code already avoided generating CFI instructions, but EHABI
unwind data is generated later from the actual instructions, so we need
to avoid using the FrameSetup and FrameDestroy flags to prevent unwind
data being generated.
Added:
llvm/test/CodeGen/ARM/machine-outliner-noreturn.mir
Modified:
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/lib/Target/ARM/ARMMachineFunctionInfo.cpp
llvm/lib/Target/ARM/ARMMachineFunctionInfo.h
llvm/lib/Target/ARM/ARMTargetMachine.cpp
llvm/lib/Target/ARM/ARMTargetMachine.h
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index b85107ec471911..a0776296b8ebc7 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -6435,20 +6435,20 @@ void ARMBaseInstrInfo::saveLROnStack(MachineBasicBlock &MBB,
MachineBasicBlock::iterator It, bool CFI,
bool Auth) const {
int Align = std::max(Subtarget.getStackAlignment().value(), uint64_t(8));
+ unsigned MIFlags = CFI ? MachineInstr::FrameSetup : 0;
assert(Align >= 8 && Align <= 256);
if (Auth) {
assert(Subtarget.isThumb2());
// Compute PAC in R12. Outlining ensures R12 is dead across the outlined
// sequence.
- BuildMI(MBB, It, DebugLoc(), get(ARM::t2PAC))
- .setMIFlags(MachineInstr::FrameSetup);
+ BuildMI(MBB, It, DebugLoc(), get(ARM::t2PAC)).setMIFlags(MIFlags);
BuildMI(MBB, It, DebugLoc(), get(ARM::t2STRD_PRE), ARM::SP)
.addReg(ARM::R12, RegState::Kill)
.addReg(ARM::LR, RegState::Kill)
.addReg(ARM::SP)
.addImm(-Align)
.add(predOps(ARMCC::AL))
- .setMIFlags(MachineInstr::FrameSetup);
+ .setMIFlags(MIFlags);
} else {
unsigned Opc = Subtarget.isThumb() ? ARM::t2STR_PRE : ARM::STR_PRE_IMM;
BuildMI(MBB, It, DebugLoc(), get(Opc), ARM::SP)
@@ -6456,7 +6456,7 @@ void ARMBaseInstrInfo::saveLROnStack(MachineBasicBlock &MBB,
.addReg(ARM::SP)
.addImm(-Align)
.add(predOps(ARMCC::AL))
- .setMIFlags(MachineInstr::FrameSetup);
+ .setMIFlags(MIFlags);
}
if (!CFI)
@@ -6511,6 +6511,7 @@ void ARMBaseInstrInfo::restoreLRFromStack(MachineBasicBlock &MBB,
MachineBasicBlock::iterator It,
bool CFI, bool Auth) const {
int Align = Subtarget.getStackAlignment().value();
+ unsigned MIFlags = CFI ? MachineInstr::FrameDestroy : 0;
if (Auth) {
assert(Subtarget.isThumb2());
// Restore return address PAC and LR.
@@ -6521,7 +6522,7 @@ void ARMBaseInstrInfo::restoreLRFromStack(MachineBasicBlock &MBB,
.addReg(ARM::SP)
.addImm(Align)
.add(predOps(ARMCC::AL))
- .setMIFlags(MachineInstr::FrameDestroy);
+ .setMIFlags(MIFlags);
// LR authentication is after the CFI instructions, below.
} else {
unsigned Opc = Subtarget.isThumb() ? ARM::t2LDR_POST : ARM::LDR_POST_IMM;
@@ -6532,7 +6533,7 @@ void ARMBaseInstrInfo::restoreLRFromStack(MachineBasicBlock &MBB,
MIB.addReg(0);
MIB.addImm(Subtarget.getStackAlignment().value())
.add(predOps(ARMCC::AL))
- .setMIFlags(MachineInstr::FrameDestroy);
+ .setMIFlags(MIFlags);
}
if (CFI) {
diff --git a/llvm/lib/Target/ARM/ARMMachineFunctionInfo.cpp b/llvm/lib/Target/ARM/ARMMachineFunctionInfo.cpp
index ec2d8f59ee9b50..a364992fab3ed5 100644
--- a/llvm/lib/Target/ARM/ARMMachineFunctionInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMMachineFunctionInfo.cpp
@@ -13,6 +13,18 @@ using namespace llvm;
void ARMFunctionInfo::anchor() {}
+yaml::ARMFunctionInfo::ARMFunctionInfo(const llvm::ARMFunctionInfo &MFI)
+ : LRSpilled(MFI.isLRSpilled()) {}
+
+void yaml::ARMFunctionInfo::mappingImpl(yaml::IO &YamlIO) {
+ MappingTraits<ARMFunctionInfo>::mapping(YamlIO, *this);
+}
+
+void ARMFunctionInfo::initializeBaseYamlFields(
+ const yaml::ARMFunctionInfo &YamlMFI) {
+ LRSpilled = YamlMFI.LRSpilled;
+}
+
static bool GetBranchTargetEnforcement(const Function &F,
const ARMSubtarget *Subtarget) {
if (!Subtarget->isMClass() || !Subtarget->hasV7Ops())
diff --git a/llvm/lib/Target/ARM/ARMMachineFunctionInfo.h b/llvm/lib/Target/ARM/ARMMachineFunctionInfo.h
index f7531ce78ccae4..b9ff3a08f998f6 100644
--- a/llvm/lib/Target/ARM/ARMMachineFunctionInfo.h
+++ b/llvm/lib/Target/ARM/ARMMachineFunctionInfo.h
@@ -15,6 +15,7 @@
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/SmallPtrSet.h"
+#include "llvm/CodeGen/MIRYamlMapping.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/IR/GlobalVariable.h"
#include "llvm/Support/ErrorHandling.h"
@@ -22,6 +23,10 @@
namespace llvm {
+namespace yaml {
+struct ARMFunctionInfo;
+} // end namespace yaml
+
class ARMSubtarget;
/// ARMFunctionInfo - This class is derived from MachineFunctionInfo and
@@ -293,8 +298,29 @@ class ARMFunctionInfo : public MachineFunctionInfo {
}
bool branchTargetEnforcement() const { return BranchTargetEnforcement; }
+
+ void initializeBaseYamlFields(const yaml::ARMFunctionInfo &YamlMFI);
};
+namespace yaml {
+struct ARMFunctionInfo final : public yaml::MachineFunctionInfo {
+ bool LRSpilled;
+
+ ARMFunctionInfo() = default;
+ ARMFunctionInfo(const llvm::ARMFunctionInfo &MFI);
+
+ void mappingImpl(yaml::IO &YamlIO) override;
+ ~ARMFunctionInfo() = default;
+};
+
+template <> struct MappingTraits<ARMFunctionInfo> {
+ static void mapping(IO &YamlIO, ARMFunctionInfo &MFI) {
+ YamlIO.mapOptional("isLRSpilled", MFI.LRSpilled);
+ }
+};
+
+} // end namespace yaml
+
} // end namespace llvm
#endif // LLVM_LIB_TARGET_ARM_ARMMACHINEFUNCTIONINFO_H
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
index deae3c9df35d0e..a99773691df123 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
@@ -30,6 +30,7 @@
#include "llvm/CodeGen/GlobalISel/Legalizer.h"
#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
+#include "llvm/CodeGen/MIRParser/MIParser.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineScheduler.h"
#include "llvm/CodeGen/Passes.h"
@@ -619,3 +620,23 @@ void ARMPassConfig::addPreEmitPass2() {
addPass(createEHContGuardCatchretPass());
}
}
+
+yaml::MachineFunctionInfo *
+ARMBaseTargetMachine::createDefaultFuncInfoYAML() const {
+ return new yaml::ARMFunctionInfo();
+}
+
+yaml::MachineFunctionInfo *
+ARMBaseTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
+ const auto *MFI = MF.getInfo<ARMFunctionInfo>();
+ return new yaml::ARMFunctionInfo(*MFI);
+}
+
+bool ARMBaseTargetMachine::parseMachineFunctionInfo(
+ const yaml::MachineFunctionInfo &MFI, PerFunctionMIParsingState &PFS,
+ SMDiagnostic &Error, SMRange &SourceRange) const {
+ const auto &YamlMFI = static_cast<const yaml::ARMFunctionInfo &>(MFI);
+ MachineFunction &MF = PFS.MF;
+ MF.getInfo<ARMFunctionInfo>()->initializeBaseYamlFields(YamlMFI);
+ return false;
+}
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.h b/llvm/lib/Target/ARM/ARMTargetMachine.h
index 1754382692baad..69d8fa8ada6498 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.h
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.h
@@ -83,6 +83,14 @@ class ARMBaseTargetMachine : public LLVMTargetMachine {
// Addrspacecasts are always noops.
return true;
}
+
+ yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const override;
+ yaml::MachineFunctionInfo *
+ convertFuncInfoToYAML(const MachineFunction &MF) const override;
+ bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &,
+ PerFunctionMIParsingState &PFS,
+ SMDiagnostic &Error,
+ SMRange &SourceRange) const override;
};
/// ARM/Thumb little endian target machine.
diff --git a/llvm/test/CodeGen/ARM/machine-outliner-noreturn.mir b/llvm/test/CodeGen/ARM/machine-outliner-noreturn.mir
new file mode 100644
index 00000000000000..cd8313f27d73c7
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/machine-outliner-noreturn.mir
@@ -0,0 +1,99 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -run-pass=machine-outliner %s -o - | FileCheck %s
+
+--- |
+ target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
+ target triple = "thumbv8.1m.main-arm-none-eabi"
+
+ @__stack_chk_guard = external dso_local global ptr
+
+ define hidden void @test1(i32 %P0, i32 %P1) {
+ entry:
+ ret void
+ }
+ define hidden void @test2(ptr %agg.result) { ret void }
+ define hidden void @test3(ptr %agg.result) { ret void }
+ define hidden void @test4(ptr %agg.result) { ret void }
+
+ declare void @noreturn(ptr, ptr, ptr) noreturn
+
+...
+---
+name: test1
+tracksRegLiveness: true
+stack:
+ - { id: 1, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$lr', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+entry_values: []
+callSites: []
+debugValueSubstitutions: []
+constants: []
+machineFunctionInfo:
+ isLRSpilled: true
+body: |
+ ; CHECK-LABEL: name: test1
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: early-clobber $sp = t2STR_PRE killed $lr, $sp, -8, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_0, implicit-def $lr, implicit $sp, implicit-def $lr, implicit-def $sp, implicit-def $r1, implicit $noreg, implicit $sp
+ ; CHECK-NEXT: $lr, $sp = t2LDR_POST $sp, 8, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: tCMPi8 killed renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: t2STRDi8 killed $r2, killed $r3, $sp, 16, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 327689 /* reguse:GPR */, killed renamable $lr
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: liveins: $r4
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: tBL 14 /* CC::al */, $noreg, @noreturn, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit undef $r0, implicit undef $r1, implicit undef $r2, implicit-def $sp
+ bb.0:
+ liveins: $lr, $r0, $r1, $r2, $r3, $r4
+
+ $r1 = t2MOVi16 target-flags(arm-lo16) @__stack_chk_guard, 14 /* CC::al */, $noreg
+ $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @__stack_chk_guard, 14 /* CC::al */, $noreg
+
+ tCMPi8 killed renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ t2STRDi8 killed $r2, killed $r3, $sp, 16, 14 /* CC::al */, $noreg
+ INLINEASM &"", 1 /* sideeffect attdialect */, 327689 /* reguse:GPR */, killed renamable $lr
+
+ bb.1:
+ liveins: $r4
+
+ bb.2:
+ tBL 14 /* CC::al */, $noreg, @noreturn, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit undef $r0, implicit undef $r1, implicit undef $r2, implicit-def $sp
+
+...
+---
+name: test2
+tracksRegLiveness: true
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: test2
+ ; CHECK: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_0, implicit-def $lr, implicit $sp, implicit-def $r1, implicit-def $lr, implicit $noreg, implicit $sp
+ $r1 = t2MOVi16 target-flags(arm-lo16) @__stack_chk_guard, 14 /* CC::al */, $noreg
+ $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @__stack_chk_guard, 14 /* CC::al */, $noreg
+...
+---
+name: test3
+tracksRegLiveness: true
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: test3
+ ; CHECK: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_0, implicit-def $lr, implicit $sp, implicit-def $r1, implicit-def $lr, implicit $noreg, implicit $sp
+ $r1 = t2MOVi16 target-flags(arm-lo16) @__stack_chk_guard, 14 /* CC::al */, $noreg
+ $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @__stack_chk_guard, 14 /* CC::al */, $noreg
+...
+---
+name: test4
+tracksRegLiveness: true
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: test4
+ ; CHECK: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_0, implicit-def $lr, implicit $sp, implicit-def $r1, implicit-def $lr, implicit $noreg, implicit $sp
+ $r1 = t2MOVi16 target-flags(arm-lo16) @__stack_chk_guard, 14 /* CC::al */, $noreg
+ $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @__stack_chk_guard, 14 /* CC::al */, $noreg
More information about the llvm-commits
mailing list