[llvm] [RISCV] Move SiFive cdiscard.d.l1 and cflush.d.l1 to their own extensions. (PR #75420)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 13 18:20:31 PST 2023
https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/75420
>From 9eabc2a6ff4c64dea5c8721ede7faac2266bcb0a Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Wed, 13 Dec 2023 17:07:46 -0800
Subject: [PATCH 1/2] [RISCV] Move SiFive cdiscard.d.l1 and cflush.d.1 to their
own extensions.
These were previously in XSfcie which is not an official SiFive
Extension name and "SiFive Custom Instruction Extension" refers
to a different feature that is not supported by LLVM today.
These extensions are prefixed with XSiFive instead of XSf because
that is what has been in SiFive's downstream toolchain for a while
making this SiFive's preferred name for these extensions.
---
llvm/docs/RISCVUsage.rst | 6 +
llvm/lib/Support/RISCVISAInfo.cpp | 4 +-
.../RISCV/Disassembler/RISCVDisassembler.cpp | 8 +-
llvm/lib/Target/RISCV/RISCVFeatures.td | 16 ++
llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td | 45 ++--
llvm/lib/Target/RISCV/RISCVProcessors.td | 4 +-
.../{xsfcie-invalid.s => xsifive-invalid.s} | 16 +-
.../RISCV/{xsfcie-valid.s => xsifive-valid.s} | 16 +-
llvm/unittests/Support/RISCVISAInfoTest.cpp | 251 +++++++++---------
9 files changed, 205 insertions(+), 161 deletions(-)
rename llvm/test/MC/RISCV/{xsfcie-invalid.s => xsifive-invalid.s} (72%)
rename llvm/test/MC/RISCV/{xsfcie-valid.s => xsifive-valid.s} (79%)
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 842ebf45305952..b58e957cc44f1c 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -283,3 +283,9 @@ The current vendor extensions supported are:
``XSfcie``
LLVM implements `version 1.0.0 of the SiFive Custom Instruction Extension (CIE) Software Specification <https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf>`_ by SiFive. All custom instruction are added as described in the specification, and the riscv-toolchain-convention document linked above. These instructions are only available for S76 processor at this time.
+
+``XSiFivecdiscarddlone``
+ LLVM implements `the SiFive cdiscard.d.l1 instruction specified in <https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf>`_ by SiFive.
+
+``XSiFivecflushdlone``
+ LLVM implements `the SiFive cflush.d.l1 instruction specified in <https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf>`_ by SiFive.
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
index 85c34dd6206307..d7fbe8507bfa39 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -81,6 +81,8 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
{"xsfvfwmaccqqq", RISCVExtensionVersion{1, 0}},
{"xsfvqmaccdod", RISCVExtensionVersion{1, 0}},
{"xsfvqmaccqoq", RISCVExtensionVersion{1, 0}},
+ {"xsifivecdiscarddlone", RISCVExtensionVersion{1, 0}},
+ {"xsifivecflushdlone", RISCVExtensionVersion{1, 0}},
{"xtheadba", RISCVExtensionVersion{1, 0}},
{"xtheadbb", RISCVExtensionVersion{1, 0}},
{"xtheadbs", RISCVExtensionVersion{1, 0}},
@@ -218,7 +220,7 @@ static void verifyTables() {
static void PrintExtension(const std::string Name, const std::string Version,
const std::string Description) {
outs() << " "
- << format(Description.empty() ? "%-20s%s\n" : "%-20s%-10s%s\n",
+ << format(Description.empty() ? "%-21s%s\n" : "%-21s%-10s%s\n",
Name.c_str(), Version.c_str(), Description.c_str());
}
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 53e2b6b4d94ea0..61640a2f810ad3 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -569,7 +569,13 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
RISCV::FeatureVendorXSfvfnrclipxfqf, DecoderTableXSfvfnrclipxfqf32,
"SiFive FP32-to-int8 Ranged Clip Instructions opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfcie, DecoderTableXSfcie32,
- "Sifive CIE custom opcode table");
+ "SiFive CIE custom opcode table");
+ TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSiFivecdiscarddlone,
+ DecoderTableXSiFivecdiscarddlone32,
+ "SiFive cdiscard.d.l1 custom opcode table");
+ TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSiFivecflushdlone,
+ DecoderTableXSiFivecflushdlone32,
+ "SiFive cflush.d.l1 custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbitmanip,
DecoderTableXCVbitmanip32,
"CORE-V Bit Manipulation custom opcode table");
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 294927aecb94b8..ef28e08ba3f087 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -820,6 +820,22 @@ def HasVendorXSfcie : Predicate<"Subtarget->hasVendorXSfcie()">,
AssemblerPredicate<(all_of FeatureVendorXSfcie),
"'XSfcie' (SiFive Custom Instruction Extension SCIE.)">;
+def FeatureVendorXSiFivecflushdlone
+ : SubtargetFeature<"xsifivecflushdlone", "HasVendorXSiFivecflushdlone", "true",
+ "'XSiFivecflushdlone' (Cache Flush/Power Down Instructions)", []>;
+def HasVendorXSiFivecflushdlone :
+ Predicate<"Subtarget->hasVendorXSiFivecflushdlone()">,
+ AssemblerPredicate<(all_of FeatureVendorXSiFivecflushdlone),
+ "'XSiFivecflushdlone' (Cache Flush/Power Down Instructions)">;
+
+def FeatureVendorXSiFivecdiscarddlone
+ : SubtargetFeature<"xsifivecdiscarddlone", "HasVendorXSiFivecdiscarddlone", "true",
+ "'XSiFivecdiscarddlone' (Cache Flush/Power Down Instructions)", []>;
+def HasVendorXSiFivecdiscarddlone :
+ Predicate<"Subtarget->hasVendorXSiFivecdiscarddlone()">,
+ AssemblerPredicate<(all_of FeatureVendorXSiFivecdiscarddlone),
+ "'XSiFivecdiscarddlone' (Cache Flush/Power Down Instructions)">;
+
def FeatureVendorXSfvqmaccdod
: SubtargetFeature<"xsfvqmaccdod", "HasVendorXSfvqmaccdod", "true",
"'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2))",
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
index fa618b437ce779..3fd8ad4720cdc8 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
@@ -657,26 +657,35 @@ let Predicates = [HasVendorXSfvfnrclipxfqf] in {
defm : VPatVFNRCLIP<"vfnrclip_x_f_qf", "VFNRCLIP_X_F_QF">;
}
-let Predicates = [HasVendorXSfcie] in {
-let hasSideEffects = 1, mayLoad = 0, mayStore = 0, DecoderNamespace = "XSfcie" in {
-def SF_CFLUSH_D_L1 : RVInstI<0b000, OPC_SYSTEM, (outs), (ins GPR:$rs1), "cflush.d.l1","$rs1">,
- Sched<[]> {
- let rd = 0;
- let imm12 = {0b1111,0b1100,0b0000};
-}
-
-def SF_CDISCARD_D_L1 : RVInstI<0b000, OPC_SYSTEM, (outs), (ins GPR:$rs1), "cdiscard.d.l1","$rs1">,
- Sched<[]> {
- let rd = 0;
- let imm12 = {0b1111,0b1100,0b0010};
-}
+let Predicates = [HasVendorXSiFivecflushdlone] in {
+ let hasSideEffects = 1, mayLoad = 0, mayStore = 0,
+ DecoderNamespace = "XSiFivecflushdlone" in
+ def SF_CFLUSH_D_L1 : RVInstI<0b000, OPC_SYSTEM, (outs), (ins GPR:$rs1),
+ "cflush.d.l1", "$rs1">, Sched<[]> {
+ let rd = 0;
+ let imm12 = {0b1111,0b1100,0b0000};
+ }
+ def : InstAlias<"cflush.d.l1", (SF_CFLUSH_D_L1 X0)>;
+} // Predicates = [HasVendorXSifivecflushdlone]
+
+let Predicates = [HasVendorXSiFivecdiscarddlone] in {
+ let hasSideEffects = 1, mayLoad = 0, mayStore = 0,
+ DecoderNamespace = "XSiFivecdiscarddlone" in
+ def SF_CDISCARD_D_L1 : RVInstI<0b000, OPC_SYSTEM, (outs), (ins GPR:$rs1),
+ "cdiscard.d.l1", "$rs1">, Sched<[]> {
+ let rd = 0;
+ let imm12 = {0b1111,0b1100,0b0010};
+ }
+ def : InstAlias<"cdiscard.d.l1", (SF_CDISCARD_D_L1 X0)>;
+} // Predicates = [HasVendorXSifivecdiscarddlone]
-def SF_CEASE : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), "cease","">, Sched<[]> {
+let Predicates = [HasVendorXSfcie] in {
+let hasSideEffects = 1, mayLoad = 0, mayStore = 0,
+ DecoderNamespace = "XSfcie" in
+def SF_CEASE : RVInstI<0b000, OPC_SYSTEM, (outs), (ins),
+ "cease", "">, Sched<[]> {
let rs1 = 0;
let rd = 0;
let imm12 = {0b0011,0b0000,0b0101};
}
-}
-def : InstAlias<"cflush.d.l1", (SF_CFLUSH_D_L1 X0)>;
-def : InstAlias<"cdiscard.d.l1", (SF_CDISCARD_D_L1 X0)>;
-} // Predicates = [HasVendorXScie]
+} // Predicates = [HasVendorXSfcie]
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 58989fd716fa0e..49612469d4b444 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -175,7 +175,9 @@ def SIFIVE_S76 : RISCVProcessorModel<"sifive-s76",
FeatureStdExtD,
FeatureStdExtC,
FeatureStdExtZihintpause,
- FeatureVendorXSfcie],
+ FeatureVendorXSfcie,
+ FeatureVendorXSiFivecflushdlone,
+ FeatureVendorXSiFivecdiscarddlone],
[TuneSiFive7]>;
def SIFIVE_U54 : RISCVProcessorModel<"sifive-u54",
diff --git a/llvm/test/MC/RISCV/xsfcie-invalid.s b/llvm/test/MC/RISCV/xsifive-invalid.s
similarity index 72%
rename from llvm/test/MC/RISCV/xsfcie-invalid.s
rename to llvm/test/MC/RISCV/xsifive-invalid.s
index a84ffeeaa054eb..591a16b4f9ace4 100644
--- a/llvm/test/MC/RISCV/xsfcie-invalid.s
+++ b/llvm/test/MC/RISCV/xsifive-invalid.s
@@ -1,22 +1,22 @@
# SCIE - SiFive Custom Instructions Extension.
-# RUN: not llvm-mc -triple riscv32 -mattr=-xsfcie < %s 2>&1 | FileCheck %s
-# RUN: not llvm-mc -triple riscv64 -mattr=-xsfcie < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv32 < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 < %s 2>&1 | FileCheck %s
cflush.d.l1 0x10 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
cdiscard.d.l1 0x10 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
-cflush.d.l1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.)
+cflush.d.l1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSiFivecflushdlone' (Cache Flush/Power Down Instructions){{$}}
-cdiscard.d.l1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.)
+cdiscard.d.l1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSiFivecdiscarddlone' (Cache Flush/Power Down Instructions){{$}}
-cflush.d.l1 x0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.)
+cflush.d.l1 x0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSiFivecflushdlone' (Cache Flush/Power Down Instructions){{$}}
-cflush.d.l1 x7 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.)
+cflush.d.l1 x7 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSiFivecflushdlone' (Cache Flush/Power Down Instructions){{$}}
-cdiscard.d.l1 x0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.)
+cdiscard.d.l1 x0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSiFivecdiscarddlone' (Cache Flush/Power Down Instructions){{$}}
-cdiscard.d.l1 x7 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.)
+cdiscard.d.l1 x7 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSiFivecdiscarddlone' (Cache Flush/Power Down Instructions){{$}}
cease x1 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
diff --git a/llvm/test/MC/RISCV/xsfcie-valid.s b/llvm/test/MC/RISCV/xsifive-valid.s
similarity index 79%
rename from llvm/test/MC/RISCV/xsfcie-valid.s
rename to llvm/test/MC/RISCV/xsifive-valid.s
index 25f743f5ed7976..2c99a6b88ec6e2 100644
--- a/llvm/test/MC/RISCV/xsfcie-valid.s
+++ b/llvm/test/MC/RISCV/xsifive-valid.s
@@ -1,17 +1,17 @@
# SCIE - SiFive Custom Instructions Extension.
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+xsfcie -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+xsfcie,+xsifivecdiscarddlone,+xsifivecflushdlone -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+xsfcie -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+xsfcie,+xsifivecdiscarddlone,+xsifivecflushdlone -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+xsfcie -riscv-no-aliases -show-encoding 2>&1 \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+xsfcie,+xsifivecdiscarddlone,+xsifivecflushdlone -riscv-no-aliases -show-encoding 2>&1 \
# RUN: | FileCheck -check-prefixes=CHECK-WARN %s
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+xsfcie -riscv-no-aliases -show-encoding 2>&1 \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+xsfcie,+xsifivecdiscarddlone,+xsifivecflushdlone -riscv-no-aliases -show-encoding 2>&1 \
# RUN: | FileCheck -check-prefixes=CHECK-WARN %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xsfcie < %s \
-# RUN: | llvm-objdump --mattr=+xsfcie -M no-aliases -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xsfcie,+xsifivecdiscarddlone,+xsifivecflushdlone < %s \
+# RUN: | llvm-objdump --mattr=+xsfcie,+xsifivecdiscarddlone,+xsifivecflushdlone -M no-aliases -d - \
# RUN: | FileCheck -check-prefix=CHECK-INST %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+xsfcie < %s \
-# RUN: | llvm-objdump --mattr=+xsfcie -M no-aliases -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+xsfcie,+xsifivecdiscarddlone,+xsifivecflushdlone < %s \
+# RUN: | llvm-objdump --mattr=+xsfcie,+xsifivecdiscarddlone,+xsifivecflushdlone -M no-aliases -d - \
# RUN: | FileCheck -check-prefix=CHECK-INST %s
# RUN: llvm-mc %s -triple=riscv64 -mcpu=sifive-s76 -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp b/llvm/unittests/Support/RISCVISAInfoTest.cpp
index 3de14907899eb6..800332447cd545 100644
--- a/llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -633,132 +633,134 @@ TEST(RiscvExtensionsHelp, CheckExtensions) {
std::string ExpectedOutput =
R"(All available -march extensions for RISC-V
- Name Version Description
- i 2.1 This is a long dummy description
- e 2.0
- m 2.0
- a 2.1
- f 2.2
- d 2.2
- c 2.0
- v 1.0
- h 1.0
- zicbom 1.0
- zicbop 1.0
- zicboz 1.0
- zicntr 2.0
- zicsr 2.0
- zifencei 2.0
- zihintntl 1.0
- zihintpause 2.0
- zihpm 2.0
- zmmul 1.0
- zawrs 1.0
- zfa 1.0
- zfh 1.0
- zfhmin 1.0
- zfinx 1.0
- zdinx 1.0
- zca 1.0
- zcb 1.0
- zcd 1.0
- zce 1.0
- zcf 1.0
- zcmp 1.0
- zcmt 1.0
- zba 1.0
- zbb 1.0
- zbc 1.0
- zbkb 1.0
- zbkc 1.0
- zbkx 1.0
- zbs 1.0
- zk 1.0
- zkn 1.0
- zknd 1.0
- zkne 1.0
- zknh 1.0
- zkr 1.0
- zks 1.0
- zksed 1.0
- zksh 1.0
- zkt 1.0
- zve32f 1.0
- zve32x 1.0
- zve64d 1.0
- zve64f 1.0
- zve64x 1.0
- zvfh 1.0
- zvfhmin 1.0
- zvl1024b 1.0
- zvl128b 1.0
- zvl16384b 1.0
- zvl2048b 1.0
- zvl256b 1.0
- zvl32768b 1.0
- zvl32b 1.0
- zvl4096b 1.0
- zvl512b 1.0
- zvl64b 1.0
- zvl65536b 1.0
- zvl8192b 1.0
- zhinx 1.0
- zhinxmin 1.0
- smaia 1.0
- ssaia 1.0
- svinval 1.0
- svnapot 1.0
- svpbmt 1.0
- xcvalu 1.0
- xcvbi 1.0
- xcvbitmanip 1.0
- xcvelw 1.0
- xcvmac 1.0
- xcvmem 1.0
- xcvsimd 1.0
- xsfcie 1.0
- xsfvcp 1.0
- xsfvfnrclipxfqf 1.0
- xsfvfwmaccqqq 1.0
- xsfvqmaccdod 1.0
- xsfvqmaccqoq 1.0
- xtheadba 1.0
- xtheadbb 1.0
- xtheadbs 1.0
- xtheadcmo 1.0
- xtheadcondmov 1.0
- xtheadfmemidx 1.0
- xtheadmac 1.0
- xtheadmemidx 1.0
- xtheadmempair 1.0
- xtheadsync 1.0
- xtheadvdot 1.0
- xventanacondops 1.0
+ Name Version Description
+ i 2.1 This is a long dummy description
+ e 2.0
+ m 2.0
+ a 2.1
+ f 2.2
+ d 2.2
+ c 2.0
+ v 1.0
+ h 1.0
+ zicbom 1.0
+ zicbop 1.0
+ zicboz 1.0
+ zicntr 2.0
+ zicsr 2.0
+ zifencei 2.0
+ zihintntl 1.0
+ zihintpause 2.0
+ zihpm 2.0
+ zmmul 1.0
+ zawrs 1.0
+ zfa 1.0
+ zfh 1.0
+ zfhmin 1.0
+ zfinx 1.0
+ zdinx 1.0
+ zca 1.0
+ zcb 1.0
+ zcd 1.0
+ zce 1.0
+ zcf 1.0
+ zcmp 1.0
+ zcmt 1.0
+ zba 1.0
+ zbb 1.0
+ zbc 1.0
+ zbkb 1.0
+ zbkc 1.0
+ zbkx 1.0
+ zbs 1.0
+ zk 1.0
+ zkn 1.0
+ zknd 1.0
+ zkne 1.0
+ zknh 1.0
+ zkr 1.0
+ zks 1.0
+ zksed 1.0
+ zksh 1.0
+ zkt 1.0
+ zve32f 1.0
+ zve32x 1.0
+ zve64d 1.0
+ zve64f 1.0
+ zve64x 1.0
+ zvfh 1.0
+ zvfhmin 1.0
+ zvl1024b 1.0
+ zvl128b 1.0
+ zvl16384b 1.0
+ zvl2048b 1.0
+ zvl256b 1.0
+ zvl32768b 1.0
+ zvl32b 1.0
+ zvl4096b 1.0
+ zvl512b 1.0
+ zvl64b 1.0
+ zvl65536b 1.0
+ zvl8192b 1.0
+ zhinx 1.0
+ zhinxmin 1.0
+ smaia 1.0
+ ssaia 1.0
+ svinval 1.0
+ svnapot 1.0
+ svpbmt 1.0
+ xcvalu 1.0
+ xcvbi 1.0
+ xcvbitmanip 1.0
+ xcvelw 1.0
+ xcvmac 1.0
+ xcvmem 1.0
+ xcvsimd 1.0
+ xsfcie 1.0
+ xsfvcp 1.0
+ xsfvfnrclipxfqf 1.0
+ xsfvfwmaccqqq 1.0
+ xsfvqmaccdod 1.0
+ xsfvqmaccqoq 1.0
+ xsifivecdiscarddlone 1.0
+ xsifivecflushdlone 1.0
+ xtheadba 1.0
+ xtheadbb 1.0
+ xtheadbs 1.0
+ xtheadcmo 1.0
+ xtheadcondmov 1.0
+ xtheadfmemidx 1.0
+ xtheadmac 1.0
+ xtheadmemidx 1.0
+ xtheadmempair 1.0
+ xtheadsync 1.0
+ xtheadvdot 1.0
+ xventanacondops 1.0
Experimental extensions
- zicfilp 0.4 This is a long dummy description
- zicond 1.0
- zacas 1.0
- zfbfmin 0.8
- ztso 0.1
- zvbb 1.0
- zvbc 1.0
- zvfbfmin 0.8
- zvfbfwma 0.8
- zvkb 1.0
- zvkg 1.0
- zvkn 1.0
- zvknc 1.0
- zvkned 1.0
- zvkng 1.0
- zvknha 1.0
- zvknhb 1.0
- zvks 1.0
- zvksc 1.0
- zvksed 1.0
- zvksg 1.0
- zvksh 1.0
- zvkt 1.0
+ zicfilp 0.4 This is a long dummy description
+ zicond 1.0
+ zacas 1.0
+ zfbfmin 0.8
+ ztso 0.1
+ zvbb 1.0
+ zvbc 1.0
+ zvfbfmin 0.8
+ zvfbfwma 0.8
+ zvkb 1.0
+ zvkg 1.0
+ zvkn 1.0
+ zvknc 1.0
+ zvkned 1.0
+ zvkng 1.0
+ zvknha 1.0
+ zvknhb 1.0
+ zvks 1.0
+ zvksc 1.0
+ zvksed 1.0
+ zvksg 1.0
+ zvksh 1.0
+ zvkt 1.0
Use -march to specify the target's extension.
For example, clang -march=rv32i_v1p0)";
@@ -774,6 +776,7 @@ For example, clang -march=rv32i_v1p0)";
outs().flush();
std::string CapturedOutput = testing::internal::GetCapturedStdout();
+ dbgs() << CapturedOutput << "\n";
EXPECT_TRUE([](std::string &Captured, std::string &Expected) {
return Captured.find(Expected) != std::string::npos;
}(CapturedOutput, ExpectedOutput));
>From 4e65008c76a97abf03f4442b6728758470940a40 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Wed, 13 Dec 2023 18:20:15 -0800
Subject: [PATCH 2/2] fixup! remove debug print
---
llvm/unittests/Support/RISCVISAInfoTest.cpp | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp b/llvm/unittests/Support/RISCVISAInfoTest.cpp
index 800332447cd545..64c4852109292e 100644
--- a/llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -776,7 +776,6 @@ For example, clang -march=rv32i_v1p0)";
outs().flush();
std::string CapturedOutput = testing::internal::GetCapturedStdout();
- dbgs() << CapturedOutput << "\n";
EXPECT_TRUE([](std::string &Captured, std::string &Expected) {
return Captured.find(Expected) != std::string::npos;
}(CapturedOutput, ExpectedOutput));
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