[llvm] [RISCV][InsertSETVTLI] Handle large immediates in backwards walk (PR #75409)

via llvm-commits llvm-commits at lists.llvm.org
Wed Dec 13 16:10:45 PST 2023


github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

<details>
<summary>
You can test this locally with the following command:
</summary>

``````````bash
git-clang-format --diff 12af9c833797b579cde97b2378cb3a3153edbed4 996406531ed86eae8b94e7fa27726ab92980a68f -- llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
``````````

</details>

<details>
<summary>
View the diff from clang-format here.
</summary>

``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index b2d36b362b..fe2bb201be 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -1461,9 +1461,8 @@ static bool isNonZeroAVL(const MachineOperand &MO,
     if (MO.getReg() == RISCV::X0)
       return true;
     if (MachineInstr *MI = MRI.getVRegDef(MO.getReg());
-        MI && MI->getOpcode() == RISCV::ADDI &&
-        MI->getOperand(1).isReg() && MI->getOperand(2).isImm() &&
-        MI->getOperand(1).getReg() == RISCV::X0 &&
+        MI && MI->getOpcode() == RISCV::ADDI && MI->getOperand(1).isReg() &&
+        MI->getOperand(2).isImm() && MI->getOperand(1).getReg() == RISCV::X0 &&
         MI->getOperand(2).getImm() != 0)
       return true;
     return false;

``````````

</details>


https://github.com/llvm/llvm-project/pull/75409


More information about the llvm-commits mailing list