[llvm] [AMDGPU] Introduce orderign parameter to atomic intrinsics and introduce new llvm.amdgcn.image.atomic.load intrinsic. (PR #73613)

[via llvm-commits]

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@@ -680,6 +680,7 @@ class AMDGPUDimProfile<string opmod,
   bit ZCompare = false;
   bit Gradients = false;
   string LodClampMip = "";
+  bit IsAtomicLoad = false;
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sstipanovic wrote:

It was helpful to work with additional parameter. When I put the ordering in cachepolicy then it will only need one check for adding `nosync`.

https://github.com/llvm/llvm-project/pull/73613