[llvm] [AArch64] ORRWrs is copy instruction when there's no implicit def of the X register (PR #75184)

[David Green via llvm-commits]

================
@@ -9180,24 +9180,46 @@ void AArch64InstrInfo::buildClearRegister(Register Reg, MachineBasicBlock &MBB,
 
 std::optional<DestSourcePair>
 AArch64InstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
-
   // AArch64::ORRWrs and AArch64::ORRXrs with WZR/XZR reg
   // and zero immediate operands used as an alias for mov instruction.
-  if (MI.getOpcode() == AArch64::ORRWrs &&
-      MI.getOperand(1).getReg() == AArch64::WZR &&
-      MI.getOperand(3).getImm() == 0x0) {
+  bool OpIsORRWrs = MI.getOpcode() == AArch64::ORRWrs;
+  bool OpIsORRXrs = MI.getOpcode() == AArch64::ORRXrs;
+  if (!(OpIsORRWrs || OpIsORRXrs) || MI.getOperand(3).getImm() != 0x0)
+    return std::nullopt;
+  Register Reg1 = MI.getOperand(1).getReg();
+
+  if (OpIsORRWrs && Reg1 == AArch64::WZR) {
+    Register Reg0 = MI.getOperand(0).getReg();
+    // ORRWrs is copy instruction when there's no implicit def of the X
+    // register.
+    if (Reg0.isPhysical()) {
----------------
davemgreen wrote:

I think this might be able to use MI.findRegisterDefOperandIdx with the Z register.
Something like this, maybe:
```
  if (MI.getOpcode() == AArch64::ORRWrs &&                                   
      MI.getOperand(1).getReg() == AArch64::WZR &&                           
      MI.getOperand(3).getImm() == 0x0 &&                                    
      // Check that the w->w move is not a zero-extending w->x mov.          
      (!MI.getOperand(0).getReg().isVirtual() ||                             
       !MI.getOperand(0).getSubReg() != 0) &&                                
      (!MI.getOperand(0).getReg().isPhysical() ||                            
       MI.findRegisterDefOperandIdx(MI.getOperand(0).getReg() - AArch64::W0 +
                                    AArch64::X0) == -1)) {                   
    return DestSourcePair{MI.getOperand(0), MI.getOperand(2)};               
```

https://github.com/llvm/llvm-project/pull/75184