[llvm] GlobalISel lane masks merging (PR #73337)

[Nicolai Hähnle via llvm-commits]

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@@ -207,9 +207,31 @@ bool AMDGPUInstructionSelector::selectCOPY(MachineInstr &I) const {
   return true;
 }
 
+bool isLaneMask(Register Reg, MachineRegisterInfo *MRI,
+                const SIRegisterInfo &TRI) {
+  if (MRI->getType(Reg) != LLT::scalar(1))
+    return false;
+  const TargetRegisterClass *RC = MRI->getRegClassOrNull(Reg);
+  return RC && TRI.isSGPRClass(RC);
+}
+
 bool AMDGPUInstructionSelector::selectPHI(MachineInstr &I) const {
   const Register DefReg = I.getOperand(0).getReg();
   const LLT DefTy = MRI->getType(DefReg);
+  // Lane mask PHIs, PHI where all register operands have sgpr register class
+  // with S1 LLT, are already selected in divergence lowering pass.
+  if (I.getOpcode() == AMDGPU::PHI && isLaneMask(DefReg, MRI, TRI)) {
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nhaehnle wrote:

Huh, I wonder if @arsenm knows where that test comes from, whether that's on purpose or perhaps a mistake and the test should be removed.

If my understanding is wrong and other PHIs are possible, it would be good to understand why. If they aren't, then the test should be removed and it's not so important to check all the operands IMHO.

https://github.com/llvm/llvm-project/pull/73337