[llvm] [AArch64][GISel] Drop custom selectors for ptrauth_* intrinsics (PR #75328)

[Anatoly Trosinenko via llvm-commits]

https://github.com/atrosinenko created https://github.com/llvm/llvm-project/pull/75328

Drop custom selector code for ptrauth_(sign|strip|blend) intrinsics from AArch64InstructionSelector::selectIntrinsic function.

The code for strip and blend intrinsics was needed because of a bug in TableGen fixed in 78623b079b3be841e96ce968ae5156fe26f6c565. The ptrauth_sign intrinsic was presumably fixed long ago.

>From cb33c0fe2a43a8ae826be8dfac19627b65dbf080 Mon Sep 17 00:00:00 2001
From: Anatoly Trosinenko <atrosinenko at accesssoftek.com>
Date: Mon, 11 Dec 2023 20:50:24 +0300
Subject: [PATCH] [AArch64][GISel] Drop custom selectors for ptrauth_*
 intrinsics

Drop custom selector code for ptrauth_(sign|strip|blend) intrinsics
from AArch64InstructionSelector::selectIntrinsic function.

The code for strip and blend intrinsics was needed because of a bug in
TableGen fixed in 78623b079b3be841e96ce968ae5156fe26f6c565. The ptrauth_sign
intrinsic was presumably fixed long ago.
---
 .../GISel/AArch64InstructionSelector.cpp      | 62 -------------------
 1 file changed, 62 deletions(-)

diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index bdaae4dd724d53..a4ace6cce46342 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -6717,68 +6717,6 @@ bool AArch64InstructionSelector::selectIntrinsic(MachineInstr &I,
     I.eraseFromParent();
     return true;
   }
-  case Intrinsic::ptrauth_sign: {
-    Register DstReg = I.getOperand(0).getReg();
-    Register ValReg = I.getOperand(2).getReg();
-    uint64_t Key = I.getOperand(3).getImm();
-    Register DiscReg = I.getOperand(4).getReg();
-    auto DiscVal = getIConstantVRegVal(DiscReg, MRI);
-    bool IsDiscZero = DiscVal && DiscVal->isZero();
-
-    if (Key > AArch64PACKey::LAST)
-      return false;
-
-    unsigned Opcodes[][4] = {
-        {AArch64::PACIA, AArch64::PACIB, AArch64::PACDA, AArch64::PACDB},
-        {AArch64::PACIZA, AArch64::PACIZB, AArch64::PACDZA, AArch64::PACDZB}};
-    unsigned Opcode = Opcodes[IsDiscZero][Key];
-
-    auto PAC = MIB.buildInstr(Opcode, {DstReg}, {ValReg});
-
-    if (!IsDiscZero) {
-      PAC.addUse(DiscReg);
-      RBI.constrainGenericRegister(DiscReg, AArch64::GPR64spRegClass, MRI);
-    }
-
-    RBI.constrainGenericRegister(DstReg, AArch64::GPR64RegClass, MRI);
-    I.eraseFromParent();
-    return true;
-  }
-  case Intrinsic::ptrauth_strip: {
-    Register DstReg = I.getOperand(0).getReg();
-    Register ValReg = I.getOperand(2).getReg();
-    uint64_t Key = I.getOperand(3).getImm();
-
-    if (Key > AArch64PACKey::LAST)
-      return false;
-    unsigned Opcode = getXPACOpcodeForKey((AArch64PACKey::ID)Key);
-
-    MIB.buildInstr(Opcode, {DstReg}, {ValReg});
-
-    RBI.constrainGenericRegister(DstReg, AArch64::GPR64RegClass, MRI);
-    RBI.constrainGenericRegister(ValReg, AArch64::GPR64RegClass, MRI);
-    I.eraseFromParent();
-    return true;
-  }
-  case Intrinsic::ptrauth_blend: {
-    MachineFunction &MF = *I.getParent()->getParent();
-    auto RHS = getIConstantVRegVal(I.getOperand(3).getReg(), MRI);
-    if (RHS && (RHS->getZExtValue() <= 0xffff)) {
-      I.setDesc(TII.get(AArch64::MOVKXi));
-      I.removeOperand(3);
-      I.removeOperand(1);
-      MachineInstrBuilder(MF, I)
-          .addImm(RHS->getZExtValue() & 0xffff)
-          .addImm(48)
-          .constrainAllUses(TII, TRI, RBI);
-    } else {
-      I.setDesc(TII.get(AArch64::BFMXri));
-      I.removeOperand(1);
-      MachineInstrBuilder(MF, I).addImm(16).addImm(15).constrainAllUses(
-          TII, TRI, RBI);
-    }
-    return true;
-  }
   case Intrinsic::frameaddress:
   case Intrinsic::returnaddress: {
     MachineFunction &MF = *I.getParent()->getParent();