[llvm] This patch fix a bug that may caused error for a self-defined target in SelectionDAG::getNode (PR #75320)

[yan zhou via llvm-commits]

https://github.com/zhou3968322 created https://github.com/llvm/llvm-project/pull/75320

we need first judge N1.getNumOperands() > 0.

If Lowering Generated SDNode like.

```
v2i32 t20:  TargetOpNode.
i32 t21: extract_vector_elt t20  0
i32 t22: extract_vector_elt t20 1
```

will cause a error.

>From b4c0c58aa5ef4b035cf28eaa7414fa92eb2e253a Mon Sep 17 00:00:00 2001
From: yan zhou <42528857+zhou3968322 at users.noreply.github.com>
Date: Wed, 13 Dec 2023 19:09:03 +0800
Subject: [PATCH] fix a bug that may caused self-defined target.

first judage N1.getNumOperands() > 0 may be better.

If Lowering Generated SDNode like.

v2i32 t20:  TargetOpNode.
i32 t21: extract_vector_elt t20 0.

will cause a error.
---
 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 5be1892a44f6dd..5720d001d2e337 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -6858,8 +6858,9 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
     // expanding copies of large vectors from registers. This only works for
     // fixed length vectors, since we need to know the exact number of
     // elements.
-    if (N2C && N1.getOperand(0).getValueType().isFixedLengthVector() &&
-        N1.getOpcode() == ISD::CONCAT_VECTORS && N1.getNumOperands() > 0) {
+    if (N2C && N1.getNumOperands() > 0 && 
+        N1.getOperand(0).getValueType().isFixedLengthVector() &&
+        N1.getOpcode() == ISD::CONCAT_VECTORS) {
       unsigned Factor =
         N1.getOperand(0).getValueType().getVectorNumElements();
       return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,