[llvm] GlobalISel lane masks merging (PR #73337)

Petar Avramovic via llvm-commits llvm-commits at lists.llvm.org
Wed Dec 13 02:41:51 PST 2023


================
@@ -207,7 +207,39 @@ bool AMDGPUInstructionSelector::selectCOPY(MachineInstr &I) const {
   return true;
 }
 
+bool isLaneMask(Register Reg, MachineRegisterInfo *MRI,
+                const SIRegisterInfo &TRI) {
+  if (MRI->getType(Reg) != LLT::scalar(1))
+    return false;
+  const TargetRegisterClass *RC = MRI->getRegClassOrNull(Reg);
+  if (!RC || !TRI.isSGPRClass(RC))
+    return false;
+
+  return true;
+}
+
+// PHI where all register operands are sgpr(register class) with S1 LLT.
+bool isLaneMaskPhi(MachineInstr &I, MachineRegisterInfo *MRI,
+                   const SIRegisterInfo &TRI) {
+  if (I.getOpcode() != AMDGPU::PHI)
----------------
petar-avramovic wrote:

> So the point is that if we see an PHI here (as opposed to a G_PHI), that's because it has already been selected.
Yes at the moment, but I did not want to be that much restrictive and put an assert.
It was meant to report selected lane mask PHI as already selected.
If it was not properly instruction selected leave it (ideally to fail selection).
There will be changes to how we select phis later so maybe then we can add some assert.
Can we inline it for now with a return?

https://github.com/llvm/llvm-project/pull/73337


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