[llvm] [X86][MC] Pre-commit test for 74713 (PR #75288)

[via llvm-commits]

https://github.com/XinWang10 updated https://github.com/llvm/llvm-project/pull/75288

>From cba372305dc5a6da58c0ab2ab65820584c90bc8e Mon Sep 17 00:00:00 2001
From: "Wang, Xin10" <xin10.wang at intel.com>
Date: Tue, 12 Dec 2023 22:52:57 -0800
Subject: [PATCH 1/2] [X86][MC] Pre-commit test for 74713

---
 llvm/test/MC/Disassembler/X86/avx-512.txt | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/llvm/test/MC/Disassembler/X86/avx-512.txt b/llvm/test/MC/Disassembler/X86/avx-512.txt
index 7c6f9d79ebd9b..508923624f1ff 100644
--- a/llvm/test/MC/Disassembler/X86/avx-512.txt
+++ b/llvm/test/MC/Disassembler/X86/avx-512.txt
@@ -58,6 +58,9 @@
 # CHECK: vmovq   %xmm19, 1016(%rdx)
 0x62 0xe1 0xfd 0x08 0x7e 0x5a 0x7f
 
+# CHECK: vcvttps2uqq    128(%ecx), %xmm1 {%k2}
+0x67 0x62 0xf1 0x7d 0x0a 0x78 0x49 0x10
+
 #####################################################
 #                MASK INSTRUCTIONS                  #
 #####################################################

>From 03e5417bff236169c1f584c528c26b6404b4b197 Mon Sep 17 00:00:00 2001
From: "Wang, Xin10" <xin10.wang at intel.com>
Date: Wed, 13 Dec 2023 00:32:51 -0800
Subject: [PATCH 2/2] add to new test file

---
 llvm/test/MC/Disassembler/X86/avx-512.txt     | 3 ---
 llvm/test/MC/Disassembler/X86/avx512dq_vl.txt | 4 ++++
 llvm/test/MC/X86/avx512dq_vl-att.s            | 3 +++
 llvm/test/MC/X86/avx512dq_vl-intel.s          | 3 +++
 4 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/llvm/test/MC/Disassembler/X86/avx-512.txt b/llvm/test/MC/Disassembler/X86/avx-512.txt
index 508923624f1ff..7c6f9d79ebd9b 100644
--- a/llvm/test/MC/Disassembler/X86/avx-512.txt
+++ b/llvm/test/MC/Disassembler/X86/avx-512.txt
@@ -58,9 +58,6 @@
 # CHECK: vmovq   %xmm19, 1016(%rdx)
 0x62 0xe1 0xfd 0x08 0x7e 0x5a 0x7f
 
-# CHECK: vcvttps2uqq    128(%ecx), %xmm1 {%k2}
-0x67 0x62 0xf1 0x7d 0x0a 0x78 0x49 0x10
-
 #####################################################
 #                MASK INSTRUCTIONS                  #
 #####################################################
diff --git a/llvm/test/MC/Disassembler/X86/avx512dq_vl.txt b/llvm/test/MC/Disassembler/X86/avx512dq_vl.txt
index c709a63d38100..8cd9ed8e46e2b 100644
--- a/llvm/test/MC/Disassembler/X86/avx512dq_vl.txt
+++ b/llvm/test/MC/Disassembler/X86/avx512dq_vl.txt
@@ -192,3 +192,7 @@
 # ATT:   vfpclassps	$123, (%rcx){1to8}, %k2 {%k7}
 # INTEL: vfpclassps	k2 {k7}, dword ptr [rcx]{1to8}, 123
 0x62,0xf3,0x7d,0x3f,0x66,0x11,0x7b
+
+# ATT: vcvttps2uqq     128(%ecx), %xmm1 {%k2}
+# INTEL: vcvttps2uqq     xmm1 {k2}, qword ptr [ecx + 128]
+0x67,0x62,0xf1,0x7d,0x0a,0x78,0x49,0x10
diff --git a/llvm/test/MC/X86/avx512dq_vl-att.s b/llvm/test/MC/X86/avx512dq_vl-att.s
index 2590a4b5ffa73..59600f726d7dd 100644
--- a/llvm/test/MC/X86/avx512dq_vl-att.s
+++ b/llvm/test/MC/X86/avx512dq_vl-att.s
@@ -144,3 +144,6 @@
 # CHECK: vfpclassps	$123, (%rcx){1to8}, %k2 {%k7}
 # CHECK: encoding: [0x62,0xf3,0x7d,0x3f,0x66,0x11,0x7b]
          vfpclassps	$123, (%rcx){1to8}, %k2 {%k7}
+# CHECK: vcvttps2uqq     128(%ecx), %xmm1 {%k2}
+# CHECK: encoding: [0x67,0x62,0xf1,0x7d,0x0a,0x78,0x49,0x10]
+         vcvttps2uqq     128(%ecx), %xmm1 {%k2}
diff --git a/llvm/test/MC/X86/avx512dq_vl-intel.s b/llvm/test/MC/X86/avx512dq_vl-intel.s
index 6604e1344fac9..71e9fc4136771 100644
--- a/llvm/test/MC/X86/avx512dq_vl-intel.s
+++ b/llvm/test/MC/X86/avx512dq_vl-intel.s
@@ -144,3 +144,6 @@
 # CHECK: vfpclassps	k2 {k7}, dword ptr [rcx]{1to8}, 123
 # CHECK: encoding: [0x62,0xf3,0x7d,0x3f,0x66,0x11,0x7b]
          vfpclassps	k2 {k7}, dword ptr [rcx]{1to8}, 123
+# CHECK: vcvttps2uqq     xmm1 {k2}, qword ptr [ecx + 128]
+# CHECK: encoding: [0x67,0x62,0xf1,0x7d,0x0a,0x78,0x49,0x10]
+         vcvttps2uqq     xmm1 {k2}, qword ptr [ecx + 128]