[llvm] [ARM][FPEnv] Lowering of fpmode intrinsics (PR #74054)

[via llvm-commits]

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@@ -375,6 +375,14 @@ class VectorType;
 
   // Bit position of rounding mode bits in FPSCR.
   const unsigned RoundingBitsPos = 22;
+
+  // Bits of floating-point status. These are NZCV flags, QC bit and cumulative
+  // FP exception bits.
+  const unsigned FPStatusBits = 0xf800009f;
+
+  // Some bits in the FPSCR are not yet defined.  They must be preserved when
+  // modifying the contents.
+  const unsigned FPReservedBits = 0x00086060;
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john-brawn-arm wrote:

This matches the value in https://sourceware.org/git/?p=glibc.git;a=blob;f=sysdeps/arm/fpu_control.h;h=cadbe927b3df20d06f6f4cf159c94e865a595885;hb=HEAD#l46, but I don't think it's right. Bit 0x80000 is the FZ16 bit, which is the same as the FZ bit but applies to fp16 values, so I think it should be considered a control bit, i.e. the value here should be 0x00006060.

https://github.com/llvm/llvm-project/pull/74054