[llvm] [X86] Rename VPERMI/VPERMT to VPERMI*Z/VPERMT*Z (PR #75192)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 12 06:41:22 PST 2023
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-x86
Author: Simon Pilgrim (RKSimon)
<details>
<summary>Changes</summary>
Add missing AVX512 Z prefix to conform to the standard naming convention and simplify matching in X86FoldTablesEmitter::addBroadcastEntry etc.
---
Patch is 62.79 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/75192.diff
8 Files Affected:
- (modified) llvm/lib/Target/X86/X86InstrAVX512.td (+39-39)
- (modified) llvm/lib/Target/X86/X86InstrInfo.cpp (+72-72)
- (modified) llvm/lib/Target/X86/X86SchedIceLake.td (+20-20)
- (modified) llvm/lib/Target/X86/X86SchedSapphireRapids.td (+32-32)
- (modified) llvm/lib/Target/X86/X86SchedSkylakeServer.td (+20-20)
- (modified) llvm/lib/Target/X86/X86ScheduleZnver4.td (+7-7)
- (modified) llvm/test/TableGen/x86-fold-tables.inc (+180-180)
- (modified) llvm/utils/TableGen/X86FoldTablesEmitter.cpp (-9)
``````````diff
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td
index 5eb893a82fcc7e..e1fe2b680b96a4 100644
--- a/llvm/lib/Target/X86/X86InstrAVX512.td
+++ b/llvm/lib/Target/X86/X86InstrAVX512.td
@@ -1624,19 +1624,19 @@ multiclass avx512_perm_i_sizes<bits<8> opc, string OpcodeStr,
X86FoldableSchedWrite sched,
AVX512VLVectorVTInfo VTInfo,
AVX512VLVectorVTInfo ShuffleMask> {
- defm NAME: avx512_perm_i<opc, OpcodeStr, sched, VTInfo.info512,
- ShuffleMask.info512>,
- avx512_perm_i_mb<opc, OpcodeStr, sched, VTInfo.info512,
- ShuffleMask.info512>, EVEX_V512;
+ defm NAME#Z: avx512_perm_i<opc, OpcodeStr, sched, VTInfo.info512,
+ ShuffleMask.info512>,
+ avx512_perm_i_mb<opc, OpcodeStr, sched, VTInfo.info512,
+ ShuffleMask.info512>, EVEX_V512;
let Predicates = [HasVLX] in {
- defm NAME#128: avx512_perm_i<opc, OpcodeStr, sched, VTInfo.info128,
- ShuffleMask.info128>,
- avx512_perm_i_mb<opc, OpcodeStr, sched, VTInfo.info128,
- ShuffleMask.info128>, EVEX_V128;
- defm NAME#256: avx512_perm_i<opc, OpcodeStr, sched, VTInfo.info256,
- ShuffleMask.info256>,
- avx512_perm_i_mb<opc, OpcodeStr, sched, VTInfo.info256,
- ShuffleMask.info256>, EVEX_V256;
+ defm NAME#Z128: avx512_perm_i<opc, OpcodeStr, sched, VTInfo.info128,
+ ShuffleMask.info128>,
+ avx512_perm_i_mb<opc, OpcodeStr, sched, VTInfo.info128,
+ ShuffleMask.info128>, EVEX_V128;
+ defm NAME#Z256: avx512_perm_i<opc, OpcodeStr, sched, VTInfo.info256,
+ ShuffleMask.info256>,
+ avx512_perm_i_mb<opc, OpcodeStr, sched, VTInfo.info256,
+ ShuffleMask.info256>, EVEX_V256;
}
}
@@ -1646,13 +1646,13 @@ multiclass avx512_perm_i_sizes_bw<bits<8> opc, string OpcodeStr,
AVX512VLVectorVTInfo Idx,
Predicate Prd> {
let Predicates = [Prd] in
- defm NAME: avx512_perm_i<opc, OpcodeStr, sched, VTInfo.info512,
- Idx.info512>, EVEX_V512;
+ defm NAME#Z: avx512_perm_i<opc, OpcodeStr, sched, VTInfo.info512,
+ Idx.info512>, EVEX_V512;
let Predicates = [Prd, HasVLX] in {
- defm NAME#128: avx512_perm_i<opc, OpcodeStr, sched, VTInfo.info128,
- Idx.info128>, EVEX_V128;
- defm NAME#256: avx512_perm_i<opc, OpcodeStr, sched, VTInfo.info256,
- Idx.info256>, EVEX_V256;
+ defm NAME#Z128: avx512_perm_i<opc, OpcodeStr, sched, VTInfo.info128,
+ Idx.info128>, EVEX_V128;
+ defm NAME#Z256: avx512_perm_i<opc, OpcodeStr, sched, VTInfo.info256,
+ Idx.info256>, EVEX_V256;
}
}
@@ -1702,9 +1702,9 @@ multiclass avx512_perm_i_lowering<string InstrStr, X86VectorVTInfo _,
}
// TODO: Should we add more casts? The vXi64 case is common due to ABI.
-defm : avx512_perm_i_lowering<"VPERMI2PS", v16f32_info, v16i32_info, v8i64_info>;
-defm : avx512_perm_i_lowering<"VPERMI2PS256", v8f32x_info, v8i32x_info, v4i64x_info>;
-defm : avx512_perm_i_lowering<"VPERMI2PS128", v4f32x_info, v4i32x_info, v2i64x_info>;
+defm : avx512_perm_i_lowering<"VPERMI2PSZ", v16f32_info, v16i32_info, v8i64_info>;
+defm : avx512_perm_i_lowering<"VPERMI2PSZ256", v8f32x_info, v8i32x_info, v4i64x_info>;
+defm : avx512_perm_i_lowering<"VPERMI2PSZ128", v4f32x_info, v4i32x_info, v2i64x_info>;
// VPERMT2
multiclass avx512_perm_t<bits<8> opc, string OpcodeStr,
@@ -1743,19 +1743,19 @@ multiclass avx512_perm_t_sizes<bits<8> opc, string OpcodeStr,
X86FoldableSchedWrite sched,
AVX512VLVectorVTInfo VTInfo,
AVX512VLVectorVTInfo ShuffleMask> {
- defm NAME: avx512_perm_t<opc, OpcodeStr, sched, VTInfo.info512,
- ShuffleMask.info512>,
- avx512_perm_t_mb<opc, OpcodeStr, sched, VTInfo.info512,
- ShuffleMask.info512>, EVEX_V512;
+ defm NAME#Z: avx512_perm_t<opc, OpcodeStr, sched, VTInfo.info512,
+ ShuffleMask.info512>,
+ avx512_perm_t_mb<opc, OpcodeStr, sched, VTInfo.info512,
+ ShuffleMask.info512>, EVEX_V512;
let Predicates = [HasVLX] in {
- defm NAME#128: avx512_perm_t<opc, OpcodeStr, sched, VTInfo.info128,
- ShuffleMask.info128>,
- avx512_perm_t_mb<opc, OpcodeStr, sched, VTInfo.info128,
- ShuffleMask.info128>, EVEX_V128;
- defm NAME#256: avx512_perm_t<opc, OpcodeStr, sched, VTInfo.info256,
- ShuffleMask.info256>,
- avx512_perm_t_mb<opc, OpcodeStr, sched, VTInfo.info256,
- ShuffleMask.info256>, EVEX_V256;
+ defm NAME#Z128: avx512_perm_t<opc, OpcodeStr, sched, VTInfo.info128,
+ ShuffleMask.info128>,
+ avx512_perm_t_mb<opc, OpcodeStr, sched, VTInfo.info128,
+ ShuffleMask.info128>, EVEX_V128;
+ defm NAME#Z256: avx512_perm_t<opc, OpcodeStr, sched, VTInfo.info256,
+ ShuffleMask.info256>,
+ avx512_perm_t_mb<opc, OpcodeStr, sched, VTInfo.info256,
+ ShuffleMask.info256>, EVEX_V256;
}
}
@@ -1764,13 +1764,13 @@ multiclass avx512_perm_t_sizes_bw<bits<8> opc, string OpcodeStr,
AVX512VLVectorVTInfo VTInfo,
AVX512VLVectorVTInfo Idx, Predicate Prd> {
let Predicates = [Prd] in
- defm NAME: avx512_perm_t<opc, OpcodeStr, sched, VTInfo.info512,
- Idx.info512>, EVEX_V512;
+ defm NAME#Z: avx512_perm_t<opc, OpcodeStr, sched, VTInfo.info512,
+ Idx.info512>, EVEX_V512;
let Predicates = [Prd, HasVLX] in {
- defm NAME#128: avx512_perm_t<opc, OpcodeStr, sched, VTInfo.info128,
- Idx.info128>, EVEX_V128;
- defm NAME#256: avx512_perm_t<opc, OpcodeStr, sched, VTInfo.info256,
- Idx.info256>, EVEX_V256;
+ defm NAME#Z128: avx512_perm_t<opc, OpcodeStr, sched, VTInfo.info128,
+ Idx.info128>, EVEX_V128;
+ defm NAME#Z256: avx512_perm_t<opc, OpcodeStr, sched, VTInfo.info256,
+ Idx.info256>, EVEX_V256;
}
}
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index 7b607c6f198c72..bc2d5ed1e17dd8 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -2138,45 +2138,45 @@ static void commuteVPTERNLOG(MachineInstr &MI, unsigned SrcOpIdx1,
// commuted.
static bool isCommutableVPERMV3Instruction(unsigned Opcode) {
#define VPERM_CASES(Suffix) \
- case X86::VPERMI2##Suffix##128rr: \
- case X86::VPERMT2##Suffix##128rr: \
- case X86::VPERMI2##Suffix##256rr: \
- case X86::VPERMT2##Suffix##256rr: \
- case X86::VPERMI2##Suffix##rr: \
- case X86::VPERMT2##Suffix##rr: \
- case X86::VPERMI2##Suffix##128rm: \
- case X86::VPERMT2##Suffix##128rm: \
- case X86::VPERMI2##Suffix##256rm: \
- case X86::VPERMT2##Suffix##256rm: \
- case X86::VPERMI2##Suffix##rm: \
- case X86::VPERMT2##Suffix##rm: \
- case X86::VPERMI2##Suffix##128rrkz: \
- case X86::VPERMT2##Suffix##128rrkz: \
- case X86::VPERMI2##Suffix##256rrkz: \
- case X86::VPERMT2##Suffix##256rrkz: \
- case X86::VPERMI2##Suffix##rrkz: \
- case X86::VPERMT2##Suffix##rrkz: \
- case X86::VPERMI2##Suffix##128rmkz: \
- case X86::VPERMT2##Suffix##128rmkz: \
- case X86::VPERMI2##Suffix##256rmkz: \
- case X86::VPERMT2##Suffix##256rmkz: \
- case X86::VPERMI2##Suffix##rmkz: \
- case X86::VPERMT2##Suffix##rmkz:
+ case X86::VPERMI2##Suffix##Z128rr: \
+ case X86::VPERMT2##Suffix##Z128rr: \
+ case X86::VPERMI2##Suffix##Z256rr: \
+ case X86::VPERMT2##Suffix##Z256rr: \
+ case X86::VPERMI2##Suffix##Zrr: \
+ case X86::VPERMT2##Suffix##Zrr: \
+ case X86::VPERMI2##Suffix##Z128rm: \
+ case X86::VPERMT2##Suffix##Z128rm: \
+ case X86::VPERMI2##Suffix##Z256rm: \
+ case X86::VPERMT2##Suffix##Z256rm: \
+ case X86::VPERMI2##Suffix##Zrm: \
+ case X86::VPERMT2##Suffix##Zrm: \
+ case X86::VPERMI2##Suffix##Z128rrkz: \
+ case X86::VPERMT2##Suffix##Z128rrkz: \
+ case X86::VPERMI2##Suffix##Z256rrkz: \
+ case X86::VPERMT2##Suffix##Z256rrkz: \
+ case X86::VPERMI2##Suffix##Zrrkz: \
+ case X86::VPERMT2##Suffix##Zrrkz: \
+ case X86::VPERMI2##Suffix##Z128rmkz: \
+ case X86::VPERMT2##Suffix##Z128rmkz: \
+ case X86::VPERMI2##Suffix##Z256rmkz: \
+ case X86::VPERMT2##Suffix##Z256rmkz: \
+ case X86::VPERMI2##Suffix##Zrmkz: \
+ case X86::VPERMT2##Suffix##Zrmkz:
#define VPERM_CASES_BROADCAST(Suffix) \
VPERM_CASES(Suffix) \
- case X86::VPERMI2##Suffix##128rmb: \
- case X86::VPERMT2##Suffix##128rmb: \
- case X86::VPERMI2##Suffix##256rmb: \
- case X86::VPERMT2##Suffix##256rmb: \
- case X86::VPERMI2##Suffix##rmb: \
- case X86::VPERMT2##Suffix##rmb: \
- case X86::VPERMI2##Suffix##128rmbkz: \
- case X86::VPERMT2##Suffix##128rmbkz: \
- case X86::VPERMI2##Suffix##256rmbkz: \
- case X86::VPERMT2##Suffix##256rmbkz: \
- case X86::VPERMI2##Suffix##rmbkz: \
- case X86::VPERMT2##Suffix##rmbkz:
+ case X86::VPERMI2##Suffix##Z128rmb: \
+ case X86::VPERMT2##Suffix##Z128rmb: \
+ case X86::VPERMI2##Suffix##Z256rmb: \
+ case X86::VPERMT2##Suffix##Z256rmb: \
+ case X86::VPERMI2##Suffix##Zrmb: \
+ case X86::VPERMT2##Suffix##Zrmb: \
+ case X86::VPERMI2##Suffix##Z128rmbkz: \
+ case X86::VPERMT2##Suffix##Z128rmbkz: \
+ case X86::VPERMI2##Suffix##Z256rmbkz: \
+ case X86::VPERMT2##Suffix##Z256rmbkz: \
+ case X86::VPERMI2##Suffix##Zrmbkz: \
+ case X86::VPERMT2##Suffix##Zrmbkz:
switch (Opcode) {
default:
@@ -2197,45 +2197,45 @@ static bool isCommutableVPERMV3Instruction(unsigned Opcode) {
// from the I opcode to the T opcode and vice versa.
static unsigned getCommutedVPERMV3Opcode(unsigned Opcode) {
#define VPERM_CASES(Orig, New) \
- case X86::Orig##128rr: \
- return X86::New##128rr; \
- case X86::Orig##128rrkz: \
- return X86::New##128rrkz; \
- case X86::Orig##128rm: \
- return X86::New##128rm; \
- case X86::Orig##128rmkz: \
- return X86::New##128rmkz; \
- case X86::Orig##256rr: \
- return X86::New##256rr; \
- case X86::Orig##256rrkz: \
- return X86::New##256rrkz; \
- case X86::Orig##256rm: \
- return X86::New##256rm; \
- case X86::Orig##256rmkz: \
- return X86::New##256rmkz; \
- case X86::Orig##rr: \
- return X86::New##rr; \
- case X86::Orig##rrkz: \
- return X86::New##rrkz; \
- case X86::Orig##rm: \
- return X86::New##rm; \
- case X86::Orig##rmkz: \
- return X86::New##rmkz;
+ case X86::Orig##Z128rr: \
+ return X86::New##Z128rr; \
+ case X86::Orig##Z128rrkz: \
+ return X86::New##Z128rrkz; \
+ case X86::Orig##Z128rm: \
+ return X86::New##Z128rm; \
+ case X86::Orig##Z128rmkz: \
+ return X86::New##Z128rmkz; \
+ case X86::Orig##Z256rr: \
+ return X86::New##Z256rr; \
+ case X86::Orig##Z256rrkz: \
+ return X86::New##Z256rrkz; \
+ case X86::Orig##Z256rm: \
+ return X86::New##Z256rm; \
+ case X86::Orig##Z256rmkz: \
+ return X86::New##Z256rmkz; \
+ case X86::Orig##Zrr: \
+ return X86::New##Zrr; \
+ case X86::Orig##Zrrkz: \
+ return X86::New##Zrrkz; \
+ case X86::Orig##Zrm: \
+ return X86::New##Zrm; \
+ case X86::Orig##Zrmkz: \
+ return X86::New##Zrmkz;
#define VPERM_CASES_BROADCAST(Orig, New) \
VPERM_CASES(Orig, New) \
- case X86::Orig##128rmb: \
- return X86::New##128rmb; \
- case X86::Orig##128rmbkz: \
- return X86::New##128rmbkz; \
- case X86::Orig##256rmb: \
- return X86::New##256rmb; \
- case X86::Orig##256rmbkz: \
- return X86::New##256rmbkz; \
- case X86::Orig##rmb: \
- return X86::New##rmb; \
- case X86::Orig##rmbkz: \
- return X86::New##rmbkz;
+ case X86::Orig##Z128rmb: \
+ return X86::New##Z128rmb; \
+ case X86::Orig##Z128rmbkz: \
+ return X86::New##Z128rmbkz; \
+ case X86::Orig##Z256rmb: \
+ return X86::New##Z256rmb; \
+ case X86::Orig##Z256rmbkz: \
+ return X86::New##Z256rmbkz; \
+ case X86::Orig##Zrmb: \
+ return X86::New##Zrmb; \
+ case X86::Orig##Zrmbkz: \
+ return X86::New##Zrmbkz;
switch (Opcode) {
VPERM_CASES(VPERMI2B, VPERMT2B)
diff --git a/llvm/lib/Target/X86/X86SchedIceLake.td b/llvm/lib/Target/X86/X86SchedIceLake.td
index e27af1433d4559..2c660fad2ec7db 100644
--- a/llvm/lib/Target/X86/X86SchedIceLake.td
+++ b/llvm/lib/Target/X86/X86SchedIceLake.td
@@ -1392,12 +1392,12 @@ def ICXWriteResGroup97 : SchedWriteRes<[ICXPort5,ICXPort015]> {
let NumMicroOps = 3;
let ReleaseAtCycles = [2,1];
}
-def: InstRW<[ICXWriteResGroup97], (instregex "VPERMI2W128rr",
- "VPERMI2W256rr",
- "VPERMI2Wrr",
- "VPERMT2W128rr",
- "VPERMT2W256rr",
- "VPERMT2Wrr")>;
+def: InstRW<[ICXWriteResGroup97], (instregex "VPERMI2WZ128rr",
+ "VPERMI2WZ256rr",
+ "VPERMI2WZrr",
+ "VPERM...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/75192
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