[llvm] [LLVM] Make use of s_flbit_i32_b64 and s_ff1_i32_b64 (PR #75158)

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``````````bash
git-clang-format --diff ef23bba6e5aecbc6008e8a9ff8740fc4b04fe814 33a76a72a342bc042f8ab1ee694944f864622a78 -- llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp llvm/lib/Target/AMDGPU/SIInstrInfo.cpp llvm/lib/Target/AMDGPU/SIInstrInfo.h
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 88a95ba9b0..a42ec8ed8d 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -6857,7 +6857,7 @@ void SIInstrInfo::moveToVALUImpl(SIInstrWorklist &Worklist,
     splitScalar64BitCountOp(Worklist, Inst, AMDGPU::S_FF1_I32_B32);
     Inst.eraseFromParent();
     return;
-  
+
   case AMDGPU::S_LSHL_B32:
     if (ST.hasOnlyRevVALUShifts()) {
       NewOpcode = AMDGPU::V_LSHLREV_B32_e64;
@@ -7843,7 +7843,9 @@ void SIInstrInfo::splitScalar64BitBFE(SIInstrWorklist &Worklist,
   addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
 }
 
-void SIInstrInfo::splitScalar64BitCountOp(SIInstrWorklist &Worklist, MachineInstr &Instr, unsigned Opcode, MachineDominatorTree *MDT) const {
+void SIInstrInfo::splitScalar64BitCountOp(SIInstrWorklist &Worklist,
+                                          MachineInstr &Instr, unsigned Opcode,
+                                          MachineDominatorTree *MDT) const {
   MachineBasicBlock &MBB = *Instr.getParent();
   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
 
@@ -7856,19 +7858,17 @@ void SIInstrInfo::splitScalar64BitCountOp(SIInstrWorklist &Worklist, MachineInst
   const MCInstrDesc &InstDesc = get(Opcode);
   bool isCtlz = Opcode == AMDGPU::S_FLBIT_I32_B32;
 
-  
-  const TargetRegisterClass *SrcRC = Src.isReg() ?
-    MRI.getRegClass(Src.getReg()) :
-    &AMDGPU::SGPR_32RegClass;
+  const TargetRegisterClass *SrcRC =
+      Src.isReg() ? MRI.getRegClass(Src.getReg()) : &AMDGPU::SGPR_32RegClass;
 
   const TargetRegisterClass *SrcSubRC =
       RI.getSubRegisterClass(SrcRC, AMDGPU::sub0);
 
-  MachineOperand SrcRegSub0 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
-                                                      AMDGPU::sub0, SrcSubRC);
-  MachineOperand SrcRegSub1 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
-                                                      AMDGPU::sub1, SrcSubRC);
-  
+  MachineOperand SrcRegSub0 =
+      buildExtractSubRegOrImm(MII, MRI, Src, SrcRC, AMDGPU::sub0, SrcSubRC);
+  MachineOperand SrcRegSub1 =
+      buildExtractSubRegOrImm(MII, MRI, Src, SrcRC, AMDGPU::sub1, SrcSubRC);
+
   Register MidReg1 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
   Register MidReg2 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
   Register MidReg3 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
@@ -7880,14 +7880,24 @@ void SIInstrInfo::splitScalar64BitCountOp(SIInstrWorklist &Worklist, MachineInst
   MachineInstr *M4 = nullptr;
 
   if (isCtlz)
-    M3 = BuildMI(MBB, MII, DL, get(AMDGPU::S_ADD_I32), MidReg3).addReg(MidReg1).addImm(32);
-  else 
-    M3 = BuildMI(MBB, MII, DL, get(AMDGPU::S_ADD_I32), MidReg3).addReg(MidReg2).addImm(32);
+    M3 = BuildMI(MBB, MII, DL, get(AMDGPU::S_ADD_I32), MidReg3)
+             .addReg(MidReg1)
+             .addImm(32);
+  else
+    M3 = BuildMI(MBB, MII, DL, get(AMDGPU::S_ADD_I32), MidReg3)
+             .addReg(MidReg2)
+             .addImm(32);
 
   if (isCtlz)
-    M4 = BuildMI(MBB, MII, DL, get(AMDGPU::V_MIN3_U32_e64), MidReg4).addReg(MidReg3).addReg(MidReg2).addImm(64);
-  else 
-    M4 = BuildMI(MBB, MII, DL, get(AMDGPU::V_MIN3_U32_e64), MidReg4).addReg(MidReg3).addReg(MidReg1).addImm(64);
+    M4 = BuildMI(MBB, MII, DL, get(AMDGPU::V_MIN3_U32_e64), MidReg4)
+             .addReg(MidReg3)
+             .addReg(MidReg2)
+             .addImm(64);
+  else
+    M4 = BuildMI(MBB, MII, DL, get(AMDGPU::V_MIN3_U32_e64), MidReg4)
+             .addReg(MidReg3)
+             .addReg(MidReg1)
+             .addImm(64);
 
   MRI.replaceRegWith(Dest.getReg(), MidReg4);
 
@@ -7895,7 +7905,7 @@ void SIInstrInfo::splitScalar64BitCountOp(SIInstrWorklist &Worklist, MachineInst
   Worklist.insert(M2);
   Worklist.insert(M3);
   Worklist.insert(M4);
-  
+
   addUsersToMoveToVALUWorklist(MidReg4, MRI, Worklist);
 }
 
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index effd891eb2..6ef19b3374 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -147,7 +147,9 @@ private:
   void splitScalar64BitBCNT(SIInstrWorklist &Worklist,
                             MachineInstr &Inst) const;
   void splitScalar64BitBFE(SIInstrWorklist &Worklist, MachineInstr &Inst) const;
-  void splitScalar64BitCountOp(SIInstrWorklist &Worklist, MachineInstr &Instr, unsigned Opcode, MachineDominatorTree *MDT = nullptr) const;
+  void splitScalar64BitCountOp(SIInstrWorklist &Worklist, MachineInstr &Instr,
+                               unsigned Opcode,
+                               MachineDominatorTree *MDT = nullptr) const;
   void movePackToVALU(SIInstrWorklist &Worklist, MachineRegisterInfo &MRI,
                       MachineInstr &Inst) const;
 

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https://github.com/llvm/llvm-project/pull/75158