[llvm] [RISCV] Rematerialize load (PR #73924)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 11 20:22:07 PST 2023
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@@ -626,7 +626,7 @@ def BGE : BranchCC_rri<0b101, "bge">;
def BLTU : BranchCC_rri<0b110, "bltu">;
def BGEU : BranchCC_rri<0b111, "bgeu">;
-let IsSignExtendingOpW = 1 in {
+let IsSignExtendingOpW = 1, isReMaterializable = 1 in {
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topperc wrote:
You missed `ld`
https://github.com/llvm/llvm-project/pull/73924
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