[llvm] [AArch64]: Added code for generating XAR instruction (PR #75085)

[Shreyansh Chouhan via llvm-commits]

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@@ -4273,6 +4275,41 @@ bool AArch64DAGToDAGISel::trySelectCastScalableToFixedLengthVector(SDNode *N) {
   return true;
 }
 
+bool AArch64DAGToDAGISel::trySelectXAR(SDNode *N) {
+  assert(N->getOpcode() == ISD::OR && "Expected OR instruction");
+
+  SDValue N0 = N->getOperand(0);
+  SDValue N1 = N->getOperand(1);
+
+  if (N0->getOpcode() != AArch64ISD::VSHL ||
+      N1->getOpcode() != AArch64ISD::VLSHR)
+    return false;
+
+  if (N0->getOperand(0) != N1->getOperand(0) ||
+      N0->getOperand(0)->getOpcode() != N1->getOperand(0)->getOpcode() ||
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BK1603 wrote:

Ah right, missed this. Resolved.

https://github.com/llvm/llvm-project/pull/75085