[llvm] [GlobalISel] Remove dead VRegs after instruction selection (PR #73892)

[Evgenii Kudriashov via llvm-commits]

e-kud wrote:

> This unfortunately looks much more intrusive and potentially detrimental to compile time than I expected. Can you collect compile time data? I don't think we can accept this generically if this regresses compile time, given that for most targets this doesn't provide any tangible codegen benefit.

Yes, it does due to indexed structures of virtual registers.

I used tramp3d-v4.cpp:
```
clang++ -fno-exceptions -Wl,-lstdc++ tramp3d-v4.cpp -target aarch64-linux-gnu --gcc-toolchain=... --sysroot=...  -O0 -fglobal-isel
```
Time results (real) 0.37% increase:
```
main 0m4.515s 0m4.517s 0m4.518s 0m4.521s 0m4.522s
PR   0m4.532s 0m4.532s 0m4.535s 0m4.538s 0m4.548s
```
`ftime-report` 2.15% increase:
```
// main
   0.1196 (  8.0%)   0.0456 (  7.0%)   0.1652 (  7.7%)   0.1655 (  7.7%)  InstructionSelect
   0.1204 (  8.0%)   0.0467 (  7.1%)   0.1671 (  7.7%)   0.1675 (  7.7%)  InstructionSelect
   0.1210 (  8.0%)   0.0435 (  6.8%)   0.1645 (  7.6%)   0.1650 (  7.6%)  InstructionSelect
   0.1211 (  8.0%)   0.0438 (  6.8%)   0.1650 (  7.6%)   0.1653 (  7.6%)  InstructionSelect
   0.1213 (  7.9%)   0.0451 (  7.1%)   0.1664 (  7.7%)   0.1667 (  7.7%)  InstructionSelect
// PR
   0.1232 (  8.1%)   0.0456 (  7.1%)   0.1688 (  7.8%)   0.1692 (  7.8%)  InstructionSelect
   0.1233 (  8.1%)   0.0456 (  7.2%)   0.1689 (  7.8%)   0.1692 (  7.8%)  InstructionSelect
   0.1236 (  8.1%)   0.0454 (  7.1%)   0.1690 (  7.8%)   0.1694 (  7.8%)  InstructionSelect
   0.1241 (  8.2%)   0.0455 (  7.1%)   0.1696 (  7.9%)   0.1700 (  7.9%)  InstructionSelect
   0.1258 (  8.2%)   0.0437 (  7.0%)   0.1695 (  7.8%)   0.1698 (  7.8%)  InstructionSelect
```

> I don't think we can accept this generically if this regresses compile time, given that for most targets this doesn't provide any tangible codegen benefit.

I have a dummy version https://github.com/e-kud/llvm-project/commit/857f6bd25979db581fc27f369ecfbdcd54b43ad8: assign the first available `RegClass` to a register if a `RegClass` is not set after instruction selection 

I think this is a matter of time when somewhere in target's backend someone iterates over all virtual registers. Then it will deteriorate into each backend problem to handle `MIR` produced by `GlobalISel` differently.

https://github.com/llvm/llvm-project/pull/73892