[llvm] [RISCV][GlobalISel] Represent RISC-V vector types using LLT scalable vectors; and legalize vectorized operations for G_ADD, G_SUB, G_AND, G_OR, and G_XOR opcodes (PR #71400)

[Jiahan Xie via llvm-commits]

https://github.com/jiahanxie353 edited https://github.com/llvm/llvm-project/pull/71400