[llvm] [AArch64]: Added code for generating XAR instruction (PR #75085)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-aarch64

Author: Shreyansh Chouhan (BK1603)

<details>
<summary>Changes</summary>

cc @<!-- -->davemgreen for review.

Fixes #<!-- -->61584

---
Full diff: https://github.com/llvm/llvm-project/pull/75085.diff


2 Files Affected:

- (modified) llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp (+39) 
- (added) llvm/test/CodeGen/AArch64/xar.ll (+22) 


``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index d05d22a7164e7..f336802fc3596 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -435,6 +435,8 @@ class AArch64DAGToDAGISel : public SelectionDAGISel {
   bool trySelectCastFixedLengthToScalableVector(SDNode *N);
   bool trySelectCastScalableToFixedLengthVector(SDNode *N);
 
+  bool trySelectXAR(SDNode *N);
+
 // Include the pieces autogenerated from the target description.
 #include "AArch64GenDAGISel.inc"
 
@@ -4273,6 +4275,41 @@ bool AArch64DAGToDAGISel::trySelectCastScalableToFixedLengthVector(SDNode *N) {
   return true;
 }
 
+bool AArch64DAGToDAGISel::trySelectXAR(SDNode *N) {
+  assert(N->getOpcode() == ISD::OR && "Expected OR instruction");
+
+  SDValue N0 = N->getOperand(0);
+  SDValue N1 = N->getOperand(1);
+
+  if (N0->getOpcode() != AArch64ISD::VSHL ||
+      N1->getOpcode() != AArch64ISD::VLSHR)
+    return false;
+
+  if (N0->getOperand(0) != N1->getOperand(0) ||
+      N0->getOperand(0)->getOpcode() != N1->getOperand(0)->getOpcode() ||
+      N1->getOperand(0)->getOpcode() != ISD::XOR)
+    return false;
+
+  SDValue XOR = N0.getOperand(0);
+  SDValue R1 = XOR.getOperand(0);
+  SDValue R2 = XOR.getOperand(1);
+
+  unsigned HsAmt = N0.getConstantOperandVal(1);
+  unsigned ShAmt = N1.getConstantOperandVal(1);
+
+  SDLoc DL = SDLoc(N0.getOperand(1));
+  SDValue Imm = CurDAG->getTargetConstant(
+      ShAmt, DL, N0.getOperand(1).getValueType(), false);
+
+  if (ShAmt + HsAmt != 64)
+    return false;
+
+  SDValue Ops[] = {R1, R2, Imm};
+  CurDAG->SelectNodeTo(N, AArch64::XAR, N0.getValueType(), Ops);
+
+  return true;
+}
+
 void AArch64DAGToDAGISel::Select(SDNode *Node) {
   // If we have a custom node, we already have selected!
   if (Node->isMachineOpcode()) {
@@ -4336,6 +4373,8 @@ void AArch64DAGToDAGISel::Select(SDNode *Node) {
   case ISD::OR:
     if (tryBitfieldInsertOp(Node))
       return;
+    if (Subtarget->hasSHA3() && trySelectXAR(Node))
+      return;
     break;
 
   case ISD::EXTRACT_SUBVECTOR: {
diff --git a/llvm/test/CodeGen/AArch64/xar.ll b/llvm/test/CodeGen/AArch64/xar.ll
new file mode 100644
index 0000000000000..c602837a6e6cb
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/xar.ll
@@ -0,0 +1,22 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc -mtriple=aarch64-none-eabi -mattr=+sha3 < %s | FileCheck --check-prefix=SHA3 %s
+; RUN: llc -mtriple=aarch64-none-eabi -mattr=-sha3 < %s | FileCheck --check-prefix=NOSHA3 %s
+
+define <2 x i64> @xar(<2 x i64> %x, <2 x i64> %y) {
+; SHA3-LABEL: xar:
+; SHA3:       // %bb.0:
+; SHA3-NEXT:    xar v0.2d, v0.2d, v1.2d, #54
+; SHA3-NEXT:    ret
+;
+; NOSHA3-LABEL: xar:
+; NOSHA3:       // %bb.0:
+; NOSHA3-NEXT:    eor v1.16b, v0.16b, v1.16b
+; NOSHA3-NEXT:    shl v0.2d, v1.2d, #10
+; NOSHA3-NEXT:    usra v0.2d, v1.2d, #54
+; NOSHA3-NEXT:    ret
+    %a = xor <2 x i64> %x, %y
+    %b = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %a, <2 x i64> %a, <2 x i64> <i64 10, i64 10>)
+    ret <2 x i64> %b
+}
+
+declare <2 x i64> @llvm.fshl.v2i64(<2 x i64>, <2 x i64>, <2 x i64>)

``````````

</details>


https://github.com/llvm/llvm-project/pull/75085