[llvm] [RISCV][GISel] Instruction select for vector G_ADD, G_SUB (PR #74114)

[Michael Maitland via llvm-commits]

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@@ -0,0 +1,556 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
+# RUN: | FileCheck -check-prefix=RV32I %s
+
+---
+name:            add_nxv1s8
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
----------------
michaelmaitland wrote:

x10 and x11 are scalar registers. You should pass `$vN` registers. Remember that LMUL 1 and fractional LMUL cases use one vector register, LMUL 2 cases use 2 vector registers and so on:

```
# LMUL 1 liveins:
liveins: $v8, $v9
# LMUL 2 liveins:
liveins: $v8, $v10
# LMUL 4 liveins:
liveins: $v8, $v12, $v16
# LMUL 8 liveins:
liveins: $v8, $v16, $v24
```

https://github.com/llvm/llvm-project/pull/74114