[llvm] [RISCV][GISel] Instruction select for vector G_ADD, G_SUB (PR #74114)

[Michael Maitland via llvm-commits]

================
@@ -0,0 +1,556 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
+# RUN: | FileCheck -check-prefix=RV32I %s
+
+---
+name:            add_nxv1s8
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV32I-LABEL: name: add_nxv1s8
+    ; RV32I: liveins: $x10, $x11
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $x10
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $x11
+    ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
+    ; RV32I-NEXT: [[PseudoVADD_VV_MF8_:%[0-9]+]]:vr = PseudoVADD_VV_MF8 [[DEF]], [[COPY]], [[COPY1]], -1, 3 /* e8 */, 3 /* ta, ma */
+    ; RV32I-NEXT: $x10 = COPY [[PseudoVADD_VV_MF8_]]
+    ; RV32I-NEXT: PseudoRET implicit $x10
+    %0:vrb(<vscale x 1 x s8>) = COPY $x10
+    %1:vrb(<vscale x 1 x s8>) = COPY $x11
+    %2:vrb(<vscale x 1 x s8>) = G_ADD %0, %1
+    $x10 = COPY %2(<vscale x 1 x s8>)
----------------
michaelmaitland wrote:

Make sure to copy to vector register, not scalar register.

https://github.com/llvm/llvm-project/pull/74114