[llvm] [SelectionDAG] Add space-optimized forms of OPC_EmitCopyToReg (PR #73293)
Wang Pengcheng via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 11 04:33:36 PST 2023
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/73293
>From d9517fb623e0658ce1856e36597689bd2f678db4 Mon Sep 17 00:00:00 2001
From: wangpc <wangpengcheng.pp at bytedance.com>
Date: Fri, 24 Nov 2023 15:35:46 +0800
Subject: [PATCH 1/3] [SelectionDAG] Add space-optimized forms of
OPC_EmitCopyToReg
These new opcodes implicitly indicate the RecNo.
The old `OPC_EmitCopyToReg2` is renamed to `OPC_EmitCopyToRegHalf`.
Overall this reduces the llc binary size with all in-tree targets by
about 33K (most are from RISCV target).
---
llvm/include/llvm/CodeGen/SelectionDAGISel.h | 8 ++++++++
.../CodeGen/SelectionDAG/SelectionDAGISel.cpp | 17 ++++++++++++++---
llvm/utils/TableGen/DAGISelMatcherEmitter.cpp | 14 ++++++++++----
3 files changed, 32 insertions(+), 7 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGISel.h b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
index aa71be5d1960f..90f3ccf352a58 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
@@ -199,7 +199,15 @@ class SelectionDAGISel : public MachineFunctionPass {
OPC_EmitMergeInputChains1_1,
OPC_EmitMergeInputChains1_2,
OPC_EmitCopyToReg,
+ OPC_EmitCopyToReg0,
+ OPC_EmitCopyToReg1,
OPC_EmitCopyToReg2,
+ OPC_EmitCopyToReg3,
+ OPC_EmitCopyToReg4,
+ OPC_EmitCopyToReg5,
+ OPC_EmitCopyToReg6,
+ OPC_EmitCopyToReg7,
+ OPC_EmitCopyToRegHalf,
OPC_EmitNodeXForm,
OPC_EmitNode,
// Space-optimized forms that implicitly encode number of result VTs.
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 2018b5f0ee29d..8e1666edb3a11 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -3610,11 +3610,22 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
}
case OPC_EmitCopyToReg:
- case OPC_EmitCopyToReg2: {
- unsigned RecNo = MatcherTable[MatcherIndex++];
+ case OPC_EmitCopyToReg0:
+ case OPC_EmitCopyToReg1:
+ case OPC_EmitCopyToReg2:
+ case OPC_EmitCopyToReg3:
+ case OPC_EmitCopyToReg4:
+ case OPC_EmitCopyToReg5:
+ case OPC_EmitCopyToReg6:
+ case OPC_EmitCopyToReg7:
+ case OPC_EmitCopyToRegHalf: {
+ unsigned RecNo =
+ Opcode >= OPC_EmitCopyToReg0 && Opcode <= OPC_EmitCopyToReg7
+ ? Opcode - OPC_EmitCopyToReg0
+ : MatcherTable[MatcherIndex++];
assert(RecNo < RecordedNodes.size() && "Invalid EmitCopyToReg");
unsigned DestPhysReg = MatcherTable[MatcherIndex++];
- if (Opcode == OPC_EmitCopyToReg2)
+ if (Opcode == OPC_EmitCopyToRegHalf)
DestPhysReg |= MatcherTable[MatcherIndex++] << 8;
if (!InputChain.getNode())
diff --git a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
index ed4be74ad0d4f..d545a012fbd77 100644
--- a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
@@ -755,14 +755,20 @@ EmitMatcher(const Matcher *N, const unsigned Indent, unsigned CurrentIdx,
const auto *C2RMatcher = cast<EmitCopyToRegMatcher>(N);
int Bytes = 3;
const CodeGenRegister *Reg = C2RMatcher->getDestPhysReg();
+ unsigned Slot = C2RMatcher->getSrcSlot();
if (Reg->EnumValue > 255) {
assert(isUInt<16>(Reg->EnumValue) && "not handled");
- OS << "OPC_EmitCopyToReg2, " << C2RMatcher->getSrcSlot() << ", "
- << "TARGET_VAL(" << getQualifiedName(Reg->TheDef) << "),\n";
+ OS << "OPC_EmitCopyToRegHalf, " << Slot << ", " << "TARGET_VAL("
+ << getQualifiedName(Reg->TheDef) << "),\n";
++Bytes;
} else {
- OS << "OPC_EmitCopyToReg, " << C2RMatcher->getSrcSlot() << ", "
- << getQualifiedName(Reg->TheDef) << ",\n";
+ if (Slot < 8) {
+ OS << "OPC_EmitCopyToReg" << Slot << ", "
+ << getQualifiedName(Reg->TheDef) << ",\n";
+ --Bytes;
+ } else
+ OS << "OPC_EmitCopyToReg, " << Slot << ", "
+ << getQualifiedName(Reg->TheDef) << ",\n";
}
return Bytes;
>From 92a30ec0ebb6a23e037f160009bc93e5f3464321 Mon Sep 17 00:00:00 2001
From: wangpc <wangpengcheng.pp at bytedance.com>
Date: Fri, 24 Nov 2023 15:55:31 +0800
Subject: [PATCH 2/3] Half -> TwoByte
---
llvm/include/llvm/CodeGen/SelectionDAGISel.h | 2 +-
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 4 ++--
llvm/utils/TableGen/DAGISelMatcherEmitter.cpp | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGISel.h b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
index 90f3ccf352a58..e4b381e8a7ef9 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
@@ -207,7 +207,7 @@ class SelectionDAGISel : public MachineFunctionPass {
OPC_EmitCopyToReg5,
OPC_EmitCopyToReg6,
OPC_EmitCopyToReg7,
- OPC_EmitCopyToRegHalf,
+ OPC_EmitCopyToRegTwoByte,
OPC_EmitNodeXForm,
OPC_EmitNode,
// Space-optimized forms that implicitly encode number of result VTs.
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 8e1666edb3a11..2456626268687 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -3618,14 +3618,14 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
case OPC_EmitCopyToReg5:
case OPC_EmitCopyToReg6:
case OPC_EmitCopyToReg7:
- case OPC_EmitCopyToRegHalf: {
+ case OPC_EmitCopyToRegTwoByte: {
unsigned RecNo =
Opcode >= OPC_EmitCopyToReg0 && Opcode <= OPC_EmitCopyToReg7
? Opcode - OPC_EmitCopyToReg0
: MatcherTable[MatcherIndex++];
assert(RecNo < RecordedNodes.size() && "Invalid EmitCopyToReg");
unsigned DestPhysReg = MatcherTable[MatcherIndex++];
- if (Opcode == OPC_EmitCopyToRegHalf)
+ if (Opcode == OPC_EmitCopyToRegTwoByte)
DestPhysReg |= MatcherTable[MatcherIndex++] << 8;
if (!InputChain.getNode())
diff --git a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
index d545a012fbd77..5dd66d4b508ef 100644
--- a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
@@ -758,7 +758,7 @@ EmitMatcher(const Matcher *N, const unsigned Indent, unsigned CurrentIdx,
unsigned Slot = C2RMatcher->getSrcSlot();
if (Reg->EnumValue > 255) {
assert(isUInt<16>(Reg->EnumValue) && "not handled");
- OS << "OPC_EmitCopyToRegHalf, " << Slot << ", " << "TARGET_VAL("
+ OS << "OPC_EmitCopyToRegTwoByte, " << Slot << ", " << "TARGET_VAL("
<< getQualifiedName(Reg->TheDef) << "),\n";
++Bytes;
} else {
>From 0e9e1028ab2341322e0e26c53261fc0f2f19550e Mon Sep 17 00:00:00 2001
From: wangpc <wangpengcheng.pp at bytedance.com>
Date: Fri, 24 Nov 2023 15:57:51 +0800
Subject: [PATCH 3/3] format
---
llvm/utils/TableGen/DAGISelMatcherEmitter.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
index 5dd66d4b508ef..18980ee7d4927 100644
--- a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
@@ -758,8 +758,8 @@ EmitMatcher(const Matcher *N, const unsigned Indent, unsigned CurrentIdx,
unsigned Slot = C2RMatcher->getSrcSlot();
if (Reg->EnumValue > 255) {
assert(isUInt<16>(Reg->EnumValue) && "not handled");
- OS << "OPC_EmitCopyToRegTwoByte, " << Slot << ", " << "TARGET_VAL("
- << getQualifiedName(Reg->TheDef) << "),\n";
+ OS << "OPC_EmitCopyToRegTwoByte, " << Slot << ", "
+ << "TARGET_VAL(" << getQualifiedName(Reg->TheDef) << "),\n";
++Bytes;
} else {
if (Slot < 8) {
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