[llvm] dd32d26 - [AMDGPU] Form V_MAD_U64_U32 from mul24 (#72393)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 11 02:38:32 PST 2023
Author: Pierre van Houtryve
Date: 2023-12-11T11:38:27+01:00
New Revision: dd32d26a37e22a3bce15ed8c21145b17ff5e1401
URL: https://github.com/llvm/llvm-project/commit/dd32d26a37e22a3bce15ed8c21145b17ff5e1401
DIFF: https://github.com/llvm/llvm-project/commit/dd32d26a37e22a3bce15ed8c21145b17ff5e1401.diff
LOG: [AMDGPU] Form V_MAD_U64_U32 from mul24 (#72393)
Fixes SWDEV-421067
Added:
Modified:
llvm/lib/Target/AMDGPU/VOP3Instructions.td
llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
index 114d33b077866a..a73042f2e411a7 100644
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -678,11 +678,22 @@ multiclass IMAD32_Pats <VOP3_Pseudo inst> {
>;
}
+// Handle cases where amdgpu-codegenprepare-mul24 made a mul24 instead of a normal mul.
+// We need to separate this because otherwise OtherPredicates would be overriden.
+class IMAD32_Mul24_Pat<VOP3_Pseudo inst>: GCNPat <
+ (i64 (add (i64 (AMDGPUmul_u24 i32:$src0, i32:$src1)), i64:$src2)),
+ (inst $src0, $src1, $src2, 0 /* clamp */)
+ >;
+
// exclude pre-GFX9 where it was slow
-let OtherPredicates = [HasNotMADIntraFwdBug], SubtargetPredicate = isGFX9Plus in
+let OtherPredicates = [HasNotMADIntraFwdBug], SubtargetPredicate = isGFX9Plus in {
defm : IMAD32_Pats<V_MAD_U64_U32_e64>;
-let OtherPredicates = [HasMADIntraFwdBug], SubtargetPredicate = isGFX11Only in
+ def : IMAD32_Mul24_Pat<V_MAD_U64_U32_e64>;
+}
+let OtherPredicates = [HasMADIntraFwdBug], SubtargetPredicate = isGFX11Only in {
defm : IMAD32_Pats<V_MAD_U64_U32_gfx11_e64>;
+ def : IMAD32_Mul24_Pat<V_MAD_U64_U32_gfx11_e64>;
+}
def VOP3_PERMLANE_Profile : VOP3_Profile<VOPProfile <[i32, i32, i32, i32]>, VOP3_OPSEL> {
let InsVOP3OpSel = (ins IntOpSelMods:$src0_modifiers, VRegSrc_32:$src0,
diff --git a/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll b/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
index 40939ee69f67e9..e2a3749c7c471d 100644
--- a/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
+++ b/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
@@ -8,8 +8,8 @@
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdpal -mcpu=gfx803 < %s | FileCheck -check-prefixes=GFX8,GFX8-SDAG %s
; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdpal -mcpu=gfx803 < %s | FileCheck -check-prefixes=GFX8,GFX8-GISEL %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GFX900,GFX9-SDAG,GFX900-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GFX900,GFX9-GISEL,GFX900-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GFX9-SDAG,GFX900-SDAG,GFX900 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL,GFX900-GISEL,GFX900 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdpal -mcpu=gfx90a < %s | FileCheck -check-prefixes=GFX9,GFX90A,GFX9-SDAG,GFX90A-SDAG %s
; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdpal -mcpu=gfx90a < %s | FileCheck -check-prefixes=GFX9,GFX90A,GFX9-GISEL,GFX90A-GISEL %s
@@ -5482,23 +5482,41 @@ define i32 @v_multi_use_mul_chain_add_other_use_all(i32 %arg, i32 %arg1, i32 %ar
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v5, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_multi_use_mul_chain_add_other_use_all:
-; GFX900: ; %bb.0: ; %bb
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_add_u32_e32 v0, 1, v0
-; GFX900-NEXT: v_mul_lo_u32 v2, v0, v1
-; GFX900-NEXT: v_add_u32_e32 v0, v2, v0
-; GFX900-NEXT: v_mul_lo_u32 v0, v0, v1
-; GFX900-NEXT: v_add_u32_e32 v1, 1, v2
-; GFX900-NEXT: v_mul_lo_u32 v5, v0, v1
-; GFX900-NEXT: global_store_dword v[3:4], v2, off
-; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: global_store_dword v[3:4], v0, off
-; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: global_store_dword v[3:4], v5, off
-; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_add_u32_e32 v0, v5, v1
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; GFX900-SDAG-LABEL: v_multi_use_mul_chain_add_other_use_all:
+; GFX900-SDAG: ; %bb.0: ; %bb
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: v_add_u32_e32 v0, 1, v0
+; GFX900-SDAG-NEXT: v_mul_lo_u32 v2, v0, v1
+; GFX900-SDAG-NEXT: v_add_u32_e32 v0, v2, v0
+; GFX900-SDAG-NEXT: v_mul_lo_u32 v0, v0, v1
+; GFX900-SDAG-NEXT: v_add_u32_e32 v1, 1, v2
+; GFX900-SDAG-NEXT: v_mul_lo_u32 v5, v0, v1
+; GFX900-SDAG-NEXT: global_store_dword v[3:4], v2, off
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0)
+; GFX900-SDAG-NEXT: global_store_dword v[3:4], v0, off
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0)
+; GFX900-SDAG-NEXT: global_store_dword v[3:4], v5, off
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0)
+; GFX900-SDAG-NEXT: v_add_u32_e32 v0, v5, v1
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-GISEL-LABEL: v_multi_use_mul_chain_add_other_use_all:
+; GFX900-GISEL: ; %bb.0: ; %bb
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_add_u32_e32 v0, 1, v0
+; GFX900-GISEL-NEXT: v_mul_lo_u32 v2, v0, v1
+; GFX900-GISEL-NEXT: v_add_u32_e32 v0, v2, v0
+; GFX900-GISEL-NEXT: v_mul_lo_u32 v0, v0, v1
+; GFX900-GISEL-NEXT: v_add_u32_e32 v1, 1, v2
+; GFX900-GISEL-NEXT: v_mul_lo_u32 v5, v0, v1
+; GFX900-GISEL-NEXT: global_store_dword v[3:4], v2, off
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX900-GISEL-NEXT: global_store_dword v[3:4], v0, off
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX900-GISEL-NEXT: global_store_dword v[3:4], v5, off
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX900-GISEL-NEXT: v_add_u32_e32 v0, v5, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-SDAG-LABEL: v_multi_use_mul_chain_add_other_use_all:
; GFX90A-SDAG: ; %bb.0: ; %bb
@@ -5686,21 +5704,37 @@ define i32 @v_multi_use_mul_chain_add_other_use_some(i32 %arg, i32 %arg1, i32 %a
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_multi_use_mul_chain_add_other_use_some:
-; GFX900: ; %bb.0: ; %bb
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_add_u32_e32 v0, 1, v0
-; GFX900-NEXT: v_mul_lo_u32 v2, v0, v1
-; GFX900-NEXT: v_add_u32_e32 v0, v2, v0
-; GFX900-NEXT: v_mul_lo_u32 v0, v0, v1
-; GFX900-NEXT: v_add_u32_e32 v1, 1, v2
-; GFX900-NEXT: v_mul_lo_u32 v0, v0, v1
-; GFX900-NEXT: global_store_dword v[3:4], v2, off
-; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: global_store_dword v[3:4], v0, off
-; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_add_u32_e32 v0, v0, v1
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; GFX900-SDAG-LABEL: v_multi_use_mul_chain_add_other_use_some:
+; GFX900-SDAG: ; %bb.0: ; %bb
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: v_add_u32_e32 v0, 1, v0
+; GFX900-SDAG-NEXT: v_mul_lo_u32 v2, v0, v1
+; GFX900-SDAG-NEXT: v_add_u32_e32 v0, v2, v0
+; GFX900-SDAG-NEXT: v_mul_lo_u32 v0, v0, v1
+; GFX900-SDAG-NEXT: v_add_u32_e32 v1, 1, v2
+; GFX900-SDAG-NEXT: v_mul_lo_u32 v0, v0, v1
+; GFX900-SDAG-NEXT: global_store_dword v[3:4], v2, off
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0)
+; GFX900-SDAG-NEXT: global_store_dword v[3:4], v0, off
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0)
+; GFX900-SDAG-NEXT: v_add_u32_e32 v0, v0, v1
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-GISEL-LABEL: v_multi_use_mul_chain_add_other_use_some:
+; GFX900-GISEL: ; %bb.0: ; %bb
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_add_u32_e32 v0, 1, v0
+; GFX900-GISEL-NEXT: v_mul_lo_u32 v2, v0, v1
+; GFX900-GISEL-NEXT: v_add_u32_e32 v0, v2, v0
+; GFX900-GISEL-NEXT: v_mul_lo_u32 v0, v0, v1
+; GFX900-GISEL-NEXT: v_add_u32_e32 v1, 1, v2
+; GFX900-GISEL-NEXT: v_mul_lo_u32 v0, v0, v1
+; GFX900-GISEL-NEXT: global_store_dword v[3:4], v2, off
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX900-GISEL-NEXT: global_store_dword v[3:4], v0, off
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX900-GISEL-NEXT: v_add_u32_e32 v0, v0, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-SDAG-LABEL: v_multi_use_mul_chain_add_other_use_some:
; GFX90A-SDAG: ; %bb.0: ; %bb
@@ -8291,7 +8325,102 @@ entry:
ret <2 x i16> %add0
}
+define i64 @mul_u24_add64(i32 %x, i32 %y, i64 %z) {
+; GFX67-LABEL: mul_u24_add64:
+; GFX67: ; %bb.0:
+; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX67-NEXT: v_mul_hi_u32_u24_e32 v4, v0, v1
+; GFX67-NEXT: v_mul_u32_u24_e32 v0, v0, v1
+; GFX67-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GFX67-NEXT: v_addc_u32_e32 v1, vcc, v4, v3, vcc
+; GFX67-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: mul_u24_add64:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_mul_hi_u32_u24_e32 v4, v0, v1
+; GFX8-NEXT: v_mul_u32_u24_e32 v0, v0, v1
+; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
+; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v4, v3, vcc
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-SDAG-LABEL: mul_u24_add64:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, v1, v[2:3]
+; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-GISEL-LABEL: mul_u24_add64:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_mul_hi_u32_u24_e32 v4, v0, v1
+; GFX9-GISEL-NEXT: v_mul_u32_u24_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
+; GFX9-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v4, v3, vcc
+; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-SDAG-LABEL: mul_u24_add64:
+; GFX10-SDAG: ; %bb.0:
+; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-SDAG-NEXT: v_mad_u64_u32 v[0:1], null, v0, v1, v[2:3]
+; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-GISEL-LABEL: mul_u24_add64:
+; GFX10-GISEL: ; %bb.0:
+; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-GISEL-NEXT: v_mul_u32_u24_e32 v4, v0, v1
+; GFX10-GISEL-NEXT: v_mul_hi_u32_u24_e32 v1, v0, v1
+; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v4, v2
+; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
+; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+ %mul = call i64 @llvm.amdgcn.mul.u24.i64(i32 %x, i32 %y)
+ %add = add i64 %mul, %z
+ ret i64 %add
+}
+
+define i64 @mul_u24_zext_add64(i32 %x, i32 %y, i64 %z) {
+; GFX67-LABEL: mul_u24_zext_add64:
+; GFX67: ; %bb.0:
+; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX67-NEXT: v_mul_u32_u24_e32 v0, v0, v1
+; GFX67-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GFX67-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc
+; GFX67-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: mul_u24_zext_add64:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_mul_u32_u24_e32 v0, v0, v1
+; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
+; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: mul_u24_zext_add64:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mul_u32_u24_e32 v0, v0, v1
+; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: mul_u24_zext_add64:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_mul_u32_u24_e32 v0, v0, v1
+; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
+; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v3, vcc_lo
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+ %mul = call i32 @llvm.amdgcn.mul.u24(i32 %x, i32 %y)
+ %mul.zext = zext i32 %mul to i64
+ %add = add i64 %mul.zext, %z
+ ret i64 %add
+}
+
+declare i64 @llvm.amdgcn.mul.u24.i64(i32, i32)
+declare i32 @llvm.amdgcn.mul.u24(i32, i32)
+
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GFX6: {{.*}}
; GFX7: {{.*}}
+; GFX900: {{.*}}
; GFX90A: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll b/llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
index d9c6fbb319019d..cf588601016007 100644
--- a/llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
+++ b/llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
@@ -444,31 +444,28 @@ define protected amdgpu_kernel void @kernel_round1(ptr addrspace(1) nocapture no
; CHECK-NEXT: s_xor_b32 s4, exec_lo, s4
; CHECK-NEXT: s_cbranch_execz .LBB0_31
; CHECK-NEXT: ; %bb.30: ; in Loop: Header=BB0_28 Depth=1
-; CHECK-NEXT: v_xor_b32_e32 v5, v60, v58
-; CHECK-NEXT: v_lshrrev_b64 v[3:4], 16, v[56:57]
-; CHECK-NEXT: v_mul_u32_u24_e32 v11, 0x180, v73
-; CHECK-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; CHECK-NEXT: v_lshrrev_b64 v[1:2], 16, v[45:46]
-; CHECK-NEXT: v_lshlrev_b32_e32 v7, 16, v5
+; CHECK-NEXT: v_xor_b32_e32 v4, v60, v58
+; CHECK-NEXT: v_lshrrev_b64 v[2:3], 16, v[56:57]
+; CHECK-NEXT: v_mad_u64_u32 v[6:7], null, 0x180, v73, s[46:47]
+; CHECK-NEXT: v_lshlrev_b32_e32 v10, 5, v0
+; CHECK-NEXT: v_lshlrev_b32_e32 v1, 16, v4
; CHECK-NEXT: v_lshlrev_b32_e32 v8, 6, v72
-; CHECK-NEXT: v_add_co_u32 v11, vcc_lo, s46, v11
-; CHECK-NEXT: v_lshlrev_b32_e32 v10, 12, v63
-; CHECK-NEXT: v_or_b32_e32 v4, v7, v4
-; CHECK-NEXT: v_mul_hi_u32_u24_e32 v7, 0x180, v73
-; CHECK-NEXT: v_xor_b32_e32 v6, v61, v59
-; CHECK-NEXT: v_lshlrev_b32_e32 v9, 16, v56
-; CHECK-NEXT: v_or3_b32 v10, v8, v10, v62
+; CHECK-NEXT: v_lshlrev_b32_e32 v9, 12, v63
+; CHECK-NEXT: v_xor_b32_e32 v5, v61, v59
+; CHECK-NEXT: v_lshlrev_b32_e32 v11, 16, v56
+; CHECK-NEXT: v_or_b32_e32 v3, v1, v3
+; CHECK-NEXT: v_lshrrev_b64 v[0:1], 16, v[45:46]
+; CHECK-NEXT: v_add_co_u32 v6, vcc_lo, v6, v10
+; CHECK-NEXT: v_or3_b32 v8, v8, v9, v62
+; CHECK-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
+; CHECK-NEXT: v_lshrrev_b64 v[4:5], 16, v[4:5]
+; CHECK-NEXT: v_or_b32_e32 v1, v11, v1
; CHECK-NEXT: ; implicit-def: $vgpr42
; CHECK-NEXT: ; implicit-def: $vgpr43
; CHECK-NEXT: ; implicit-def: $vgpr44
-; CHECK-NEXT: v_add_co_ci_u32_e32 v12, vcc_lo, s47, v7, vcc_lo
-; CHECK-NEXT: v_add_co_u32 v7, vcc_lo, v11, v0
-; CHECK-NEXT: v_lshrrev_b64 v[5:6], 16, v[5:6]
-; CHECK-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, 0, v12, vcc_lo
-; CHECK-NEXT: v_or_b32_e32 v2, v9, v2
-; CHECK-NEXT: global_store_dword v[7:8], v10, off offset:4
-; CHECK-NEXT: global_store_dwordx4 v[7:8], v[1:4], off offset:8
-; CHECK-NEXT: global_store_dwordx2 v[7:8], v[5:6], off offset:24
+; CHECK-NEXT: global_store_dword v[6:7], v8, off offset:4
+; CHECK-NEXT: global_store_dwordx4 v[6:7], v[0:3], off offset:8
+; CHECK-NEXT: global_store_dwordx2 v[6:7], v[4:5], off offset:24
; CHECK-NEXT: .LBB0_31: ; %Flow
; CHECK-NEXT: ; in Loop: Header=BB0_28 Depth=1
; CHECK-NEXT: s_andn2_saveexec_b32 s4, s4
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