[llvm] [MemCpyOpt] Don't perform call slot opt if alloc type is scalable (PR #75027)

[Wang Pengcheng via llvm-commits]

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/75027

This fixes #75010.


>From edc8e636d1d31ed0b2f0c9a47853a47773301176 Mon Sep 17 00:00:00 2001
From: wangpc <wangpengcheng.pp at bytedance.com>
Date: Mon, 11 Dec 2023 14:43:02 +0800
Subject: [PATCH] [MemCpyOpt] Don't perform call slot opt if alloc type is
 scalable

This fixes #75010.
---
 .../lib/Transforms/Scalar/MemCpyOptimizer.cpp |  7 +++++--
 llvm/test/Transforms/MemCpyOpt/pr75010.ll     | 19 +++++++++++++++++++
 2 files changed, 24 insertions(+), 2 deletions(-)
 create mode 100644 llvm/test/Transforms/MemCpyOpt/pr75010.ll

diff --git a/llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp b/llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
index 0e55249d63a829..9d058e0d248378 100644
--- a/llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
+++ b/llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
@@ -880,8 +880,11 @@ bool MemCpyOptPass::performCallSlotOptzn(Instruction *cpyLoad,
     return false;
 
   const DataLayout &DL = cpyLoad->getModule()->getDataLayout();
-  uint64_t srcSize = DL.getTypeAllocSize(srcAlloca->getAllocatedType()) *
-                     srcArraySize->getZExtValue();
+  TypeSize SrcAllocaSize = DL.getTypeAllocSize(srcAlloca->getAllocatedType());
+  // We can't optimize scalable types.
+  if (SrcAllocaSize.isScalable())
+    return false;
+  uint64_t srcSize = SrcAllocaSize * srcArraySize->getZExtValue();
 
   if (cpySize < srcSize)
     return false;
diff --git a/llvm/test/Transforms/MemCpyOpt/pr75010.ll b/llvm/test/Transforms/MemCpyOpt/pr75010.ll
new file mode 100644
index 00000000000000..c9af7543b42e64
--- /dev/null
+++ b/llvm/test/Transforms/MemCpyOpt/pr75010.ll
@@ -0,0 +1,19 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -passes=memcpyopt < %s | FileCheck %s
+
+define void @f(ptr nocapture noundef writeonly %r, <vscale x 2 x i32> %x) {
+; CHECK-LABEL: @f(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[X_ADDR:%.*]] = alloca <vscale x 2 x i32>, align 8
+; CHECK-NEXT:    store <vscale x 2 x i32> [[X:%.*]], ptr [[X_ADDR]], align 8
+; CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr [[X_ADDR]], align 8
+; CHECK-NEXT:    store i64 [[TMP0]], ptr [[R:%.*]], align 1
+; CHECK-NEXT:    ret void
+;
+entry:
+  %x.addr = alloca <vscale x 2 x i32>, align 8
+  store <vscale x 2 x i32> %x, ptr %x.addr, align 8
+  %0 = load i64, ptr %x.addr, align 8
+  store i64 %0, ptr %r, align 1
+  ret void
+}